forked from OSchip/llvm-project
[X86][MMX] Regenerated vector insertion test.
Shows the true horror of what is going on.... llvm-svn: 256713
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=x86 -mattr=+mmx,+sse4.2 -mtriple=i686-apple-darwin9 | FileCheck %s
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; MMX insertelement is not available; these are promoted to XMM.
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; (Without SSE they are split to two ints, and the code is much better.)
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define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
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entry:
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; CHECK: mmx_movzl
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; CHECK: pinsrd
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; CHECK: pinsrd
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%tmp = bitcast x86_mmx %x to <2 x i32>
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%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0 ; <<2 x i32>> [#uses=1]
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%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1 ; <<2 x i32>> [#uses=1]
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%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
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ret x86_mmx %tmp9
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define x86_mmx @mmx_movzl(x86_mmx %x) nounwind {
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; CHECK-LABEL: mmx_movzl:
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; CHECK: ## BB#0:
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; CHECK-NEXT: subl $20, %esp
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; CHECK-NEXT: movq %mm0, {{[0-9]+}}(%esp)
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: movl $32, %eax
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; CHECK-NEXT: pinsrd $0, %eax, %xmm0
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: pinsrd $1, %eax, %xmm0
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; CHECK-NEXT: pinsrd $2, %eax, %xmm0
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; CHECK-NEXT: pinsrd $3, %eax, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; CHECK-NEXT: movq %xmm0, (%esp)
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; CHECK-NEXT: movq (%esp), %mm0
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; CHECK-NEXT: addl $20, %esp
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; CHECK-NEXT: retl
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%tmp = bitcast x86_mmx %x to <2 x i32>
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%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0 ; <<2 x i32>> [#uses=1]
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%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1 ; <<2 x i32>> [#uses=1]
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%tmp9 = bitcast <2 x i32> %tmp8 to x86_mmx
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ret x86_mmx %tmp9
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}
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