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[x86] Simplify detection of jcxz/jecxz/jrcxz in disassembler. 

llvm-svn: 225035
This commit is contained in:
Craig Topper 2014-12-31 07:07:11 +00:00
parent f89dc3edc9
commit 6e518776e3
1 changed files with 5 additions and 16 deletions
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21
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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@ -975,27 +975,16 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
if (insn->rexPrefix & 0x08)
attrMask |= ATTR_REXW;
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
/*
* JCXZ/JECXZ need special handling for 16-bit mode because the meaning
* of the AdSize prefix is inverted w.r.t. 32-bit mode.
*/
if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
const struct InstructionSpecifier *spec;
spec = specifierForUID(instructionID);
if (insn->mode == MODE_16BIT && insn->opcodeType == ONEBYTE &&
insn->opcode == 0xE3)
attrMask ^= ATTR_ADSIZE;
/*
* Check for Ii8PCRel instructions. We could alternatively do a
* string-compare on the names, but this is probably cheaper.
*/
if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
attrMask ^= ATTR_ADSIZE;
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
}
}
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
/* The following clauses compensate for limitations of the tables. */