forked from OSchip/llvm-project
ARM/MC: Mark several '...S' instructions as codegen only, they aren't real
instructions but are restricted pseudo forms. llvm-svn: 123176
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@ -617,7 +617,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
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/// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AI1_bin_s_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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PatFrag opnode, bit Commutable = 0> {
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@ -852,7 +852,7 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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}
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// Carry setting variants
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let Defs = [CPSR] in {
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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bit Commutable = 0> {
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def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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@ -2067,6 +2067,8 @@ defm ADC : AI1_adde_sube_irs<0b0101, "adc",
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BinOpFrag<(adde_dead_carry node:$LHS, node:$RHS)>, 1>;
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defm SBC : AI1_adde_sube_irs<0b0110, "sbc",
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BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
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// ADC and SUBC with 's' bit set.
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defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
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BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
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defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
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@ -2112,7 +2114,7 @@ def RSBrs : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
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}
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// RSB with 's' bit set.
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let Defs = [CPSR] in {
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let isCodeGenOnly = 1, Defs = [CPSR] in {
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def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
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IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
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@ -2181,7 +2183,7 @@ def RSCrs : AsI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
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}
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// FIXME: Allow these to be predicated.
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let Defs = [CPSR], Uses = [CPSR] in {
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let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
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def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
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