forked from OSchip/llvm-project
AMDGPU: Fix SI_IF lowering when the save exec reg has terminator uses
Reverts part of 6524a7a2b9. Since that
commit, the expansion was ignoring the actual save exec register
produced by the instruction, and looking at other instructions. I do
not understand why it was looking at other instructions, but relying
on this scan was wrong.
Fixes verifier errors after SI_IF is tail duplicated, which should be
correct to do. The results were fed into a phi, which was lowered to
the S_MOV_B64_term instructions.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
29e646fe65
commit
6e1770821f
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@ -98,8 +98,6 @@ private:
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void emitLoop(MachineInstr &MI);
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void emitEndCf(MachineInstr &MI);
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Register getSaveExec(MachineInstr* MI);
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void findMaskOperands(MachineInstr &MI, unsigned OpNo,
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SmallVectorImpl<MachineOperand> &Src) const;
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@ -177,29 +175,11 @@ static bool isSimpleIf(const MachineInstr &MI, const MachineRegisterInfo *MRI,
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return true;
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}
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Register SILowerControlFlow::getSaveExec(MachineInstr *MI) {
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MachineBasicBlock *MBB = MI->getParent();
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MachineOperand &SaveExec = MI->getOperand(0);
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assert(SaveExec.getSubReg() == AMDGPU::NoSubRegister);
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Register SaveExecReg = SaveExec.getReg();
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unsigned FalseTermOpc =
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TII->isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term;
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MachineBasicBlock::iterator I = (MI);
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MachineBasicBlock::iterator J = std::next(I);
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if (J != MBB->end() && J->getOpcode() == FalseTermOpc &&
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J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
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SaveExecReg = J->getOperand(0).getReg();
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J->eraseFromParent();
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}
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return SaveExecReg;
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}
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void SILowerControlFlow::emitIf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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MachineBasicBlock::iterator I(&MI);
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Register SaveExecReg = getSaveExec(&MI);
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Register SaveExecReg = MI.getOperand(0).getReg();
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MachineOperand& Cond = MI.getOperand(1);
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assert(Cond.getSubReg() == AMDGPU::NoSubRegister);
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@ -282,7 +262,7 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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Register DstReg = getSaveExec(&MI);
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Register DstReg = MI.getOperand(0).getReg();
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bool ExecModified = MI.getOperand(3).getImm() != 0;
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MachineBasicBlock::iterator Start = MBB.begin();
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@ -354,7 +334,7 @@ void SILowerControlFlow::emitElse(MachineInstr &MI) {
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void SILowerControlFlow::emitIfBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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const DebugLoc &DL = MI.getDebugLoc();
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auto Dst = getSaveExec(&MI);
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auto Dst = MI.getOperand(0).getReg();
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// Skip ANDing with exec if the break condition is already masked by exec
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// because it is a V_CMP in the same basic block. (We know the break
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@ -0,0 +1,75 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=si-lower-control-flow -verify-machineinstrs -o - %s | FileCheck %s
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# The save exec result register of SI_IF is used by other terminators
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# inserted to behave as a lowered phi. The output register of SI_IF
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# was ignored, and the def was removed, so the S_MOV_B64_term uses
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# would fail the verifier.
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---
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name: si_if_use
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alignment: 1
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legalized: true
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regBankSelected: true
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selected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: si_if_use
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY killed $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed $vgpr1
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; CHECK: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 killed [[COPY]], killed [[COPY1]], implicit $exec
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; CHECK: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; CHECK: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
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; CHECK: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
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; CHECK: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
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; CHECK: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; CHECK: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
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; CHECK: [[S_MOV_B64_term1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
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; CHECK: S_BRANCH %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[COPY3:%[0-9]+]]:sreg_64_xexec = COPY [[S_MOV_B64_term1]]
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; CHECK: dead %7:vgpr_32 = GLOBAL_LOAD_DWORD undef %8:vreg_64, 0, 0, 0, 0, implicit $exec :: (volatile load 4, addrspace 1)
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; CHECK: [[COPY4:%[0-9]+]]:sreg_64_xexec = COPY [[COPY3]]
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; CHECK: bb.2:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: [[COPY5:%[0-9]+]]:sreg_64_xexec = COPY [[COPY4]]
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; CHECK: $exec = S_OR_B64 $exec, killed [[COPY5]], implicit-def $scc
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; CHECK: S_SLEEP 1
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; CHECK: [[COPY6:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
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; CHECK: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY6]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
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; CHECK: [[S_XOR_B64_1:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_1]], [[COPY6]], implicit-def dead $scc
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; CHECK: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
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; CHECK: S_CBRANCH_EXECZ %bb.1, implicit $exec
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; CHECK: [[S_MOV_B64_term1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_1]], implicit $exec
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; CHECK: [[S_MOV_B64_term2:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_1]], implicit $exec
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; CHECK: S_BRANCH %bb.2
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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%0:vgpr_32 = COPY killed $vgpr0
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%1:vgpr_32 = COPY killed $vgpr1
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%3:sreg_64_xexec = V_CMP_EQ_U32_e64 killed %0, killed %1, implicit $exec
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%10:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
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%14:sreg_64_xexec = S_MOV_B64_term %10, implicit $exec
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%13:sreg_64_xexec = S_MOV_B64_term %10, implicit $exec
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S_BRANCH %bb.2
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bb.1:
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%11:sreg_64_xexec = COPY %13
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dead %6:vgpr_32 = GLOBAL_LOAD_DWORD undef %8:vreg_64, 0, 0, 0, 0, implicit $exec :: (volatile load 4, addrspace 1)
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%14:sreg_64_xexec = COPY %11
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bb.2:
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%12:sreg_64_xexec = COPY %14
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SI_END_CF killed %12, implicit-def $exec, implicit-def dead $scc, implicit $exec
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S_SLEEP 1
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%9:sreg_64_xexec = SI_IF %3, %bb.1, implicit-def $exec, implicit-def dead $scc, implicit $exec
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%14:sreg_64_xexec = S_MOV_B64_term %9, implicit $exec
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%13:sreg_64_xexec = S_MOV_B64_term %9, implicit $exec
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S_BRANCH %bb.2
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...
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