diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index 25cc652dbd9e..41a6fca75a56 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -450,3 +450,8 @@ def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
                                                      QFPRegs:$rs2)>,
                 Requires<[HasHardQuad]>;
 
+// signx rd -> sra rd, %g0, rd
+def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
+
+// signx reg, rd -> sra reg, %g0, rd
+def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
index e2cb87e06303..6125469b8e8c 100644
--- a/llvm/test/MC/Sparc/sparcv9-instructions.s
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -26,3 +26,12 @@
         ! V9:      popc %g1, %g2                ! encoding: [0x85,0x70,0x00,0x01]
         popc %g1, %g2
 
+
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: signx %g1, %g2
+        ! V9: sra %g1, %g0, %g2               ! encoding: [0x85,0x38,0x40,0x00]
+        signx %g1, %g2
+        ! V8:      error: instruction requires a CPU feature not currently enabled
+        ! V8-NEXT: signx %g1
+        ! V9: sra %g1, %g0, %g1               ! encoding: [0x83,0x38,0x40,0x00]
+        signx %g1