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[DAGTypeLegalizer] Handle ZERO_EXTEND of promoted type in WidenVecRes_Convert. 

On SystemZ, a ZERO_EXTEND of an i1 vector handled by WidenVecRes_Convert()
always ended up being scalarized, because the type action of the input is
promotion which was previously an unhandled case in this method.

This fixes https://bugs.llvm.org/show_bug.cgi?id=47132.

Differential Revision: https://reviews.llvm.org/D86268

Patch by Eli Friedman.
Review: Ulrich Weigand
This commit is contained in:
Jonas Paulsson 2020-08-19 12:01:03 +02:00
parent 32ae37b038
commit 6dc3e22b57
2 changed files with 35 additions and 4 deletions
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23
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -3307,19 +3307,34 @@ SDValue DAGTypeLegalizer::WidenVecRes_OverflowOp(SDNode *N, unsigned ResNo) {
}
SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
LLVMContext &Ctx = *DAG.getContext();
SDValue InOp = N->getOperand(0);
SDLoc DL(N);
EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
EVT WidenVT = TLI.getTypeToTransformTo(Ctx, N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
EVT InVT = InOp.getValueType();
EVT InEltVT = InVT.getVectorElementType();
EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
unsigned Opcode = N->getOpcode();
unsigned InVTNumElts = InVT.getVectorNumElements();
const SDNodeFlags Flags = N->getFlags();
// Handle the case of ZERO_EXTEND where the promoted InVT element size does
// not equal that of WidenVT.
if (N->getOpcode() == ISD::ZERO_EXTEND &&
getTypeAction(InVT) == TargetLowering::TypePromoteInteger &&
TLI.getTypeToTransformTo(Ctx, InVT).getScalarSizeInBits() !=
WidenVT.getScalarSizeInBits()) {
InOp = ZExtPromotedInteger(InOp);
InVT = InOp.getValueType();
if (WidenVT.getScalarSizeInBits() < InVT.getScalarSizeInBits())
Opcode = ISD::TRUNCATE;
}
EVT InEltVT = InVT.getVectorElementType();
EVT InWidenVT = EVT::getVectorVT(Ctx, InEltVT, WidenNumElts);
unsigned InVTNumElts = InVT.getVectorNumElements();
if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
InOp = GetWidenedVector(N->getOperand(0));
InVT = InOp.getValueType();

16
llvm/test/CodeGen/SystemZ/vec-zext.ll
View File

@ -92,3 +92,19 @@ define <8 x i16> @fun10(<8 x i8> %val1) {
ret <8 x i16> %z
}
define <2 x i32> @fun11(<2 x i64> %Arg1, <2 x i64> %Arg2) {
; CHECK-LABEL: fun11:
; CHECK: vgbm %v0, 0
; CHECK-NEXT: vceqg %v1, %v24, %v0
; CHECK-NEXT: vceqg %v0, %v26, %v0
; CHECK-NEXT: vo %v0, %v1, %v0
; CHECK-NEXT: vrepig %v1, 1
; CHECK-NEXT: vn %v0, %v0, %v1
; CHECK-NEXT: vpkg %v24, %v0, %v0
; CHECK-NEXT: br %r14
%i3 = icmp eq <2 x i64> %Arg1, zeroinitializer
%i5 = icmp eq <2 x i64> %Arg2, zeroinitializer
%i6 = or <2 x i1> %i3, %i5
%i7 = zext <2 x i1> %i6 to <2 x i32>
ret <2 x i32> %i7
}