[ARM GlobalISel] Clean up binary operator tests. NFC

Remove some of the instruction selector tests for binary operators (and,
or, xor). These are all derived from the same kind of TableGen pattern,
AsI1_bin_irs, so there's no point in testing all of them.

llvm-svn: 318642
This commit is contained in:
Diana Picus 2017-11-20 10:35:35 +00:00
parent 115f68ea3e
commit 6db48f7d6b
1 changed files with 0 additions and 94 deletions
llvm/test/CodeGen/ARM/GlobalISel

View File

@ -25,10 +25,6 @@
define void @test_sdiv_s32() #2 { ret void }
define void @test_udiv_s32() #2 { ret void }
define void @test_and_s32() { ret void }
define void @test_or_s32() { ret void }
define void @test_xor_s32() { ret void }
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_shl_s32() { ret void }
@ -595,96 +591,6 @@ body: |
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_and_s32
# CHECK-LABEL: name: test_and_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_AND %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = ANDrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_or_s32
# CHECK-LABEL: name: test_or_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_OR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = ORRrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_xor_s32
# CHECK-LABEL: name: test_xor_s32
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
body: |
bb.0:
liveins: %r0, %r1
%0(s32) = COPY %r0
; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
%1(s32) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
%2(s32) = G_XOR %0, %1
; CHECK: [[VREGRES:%[0-9]+]]:gpr = EORrr [[VREGX]], [[VREGY]], 14, _
%r0 = COPY %2(s32)
; CHECK: %r0 = COPY [[VREGRES]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
...
---
name: test_lshr_s32
# CHECK-LABEL: name: test_lshr_s32
legalized: true