forked from OSchip/llvm-project
[ARM GlobalISel] Clean up binary operator tests. NFC
Remove some of the instruction selector tests for binary operators (and, or, xor). These are all derived from the same kind of TableGen pattern, AsI1_bin_irs, so there's no point in testing all of them. llvm-svn: 318642
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llvm/test/CodeGen/ARM/GlobalISel
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@ -25,10 +25,6 @@
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define void @test_sdiv_s32() #2 { ret void }
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define void @test_udiv_s32() #2 { ret void }
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define void @test_and_s32() { ret void }
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define void @test_or_s32() { ret void }
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define void @test_xor_s32() { ret void }
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define void @test_lshr_s32() { ret void }
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define void @test_ashr_s32() { ret void }
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define void @test_shl_s32() { ret void }
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@ -595,96 +591,6 @@ body: |
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_and_s32
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# CHECK-LABEL: name: test_and_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
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%1(s32) = COPY %r1
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; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
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%2(s32) = G_AND %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gpr = ANDrr [[VREGX]], [[VREGY]], 14, _
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%r0 = COPY %2(s32)
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; CHECK: %r0 = COPY [[VREGRES]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_or_s32
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# CHECK-LABEL: name: test_or_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
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%1(s32) = COPY %r1
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; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
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%2(s32) = G_OR %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gpr = ORRrr [[VREGX]], [[VREGY]], 14, _
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%r0 = COPY %2(s32)
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; CHECK: %r0 = COPY [[VREGRES]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_xor_s32
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# CHECK-LABEL: name: test_xor_s32
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legalized: true
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regBankSelected: true
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selected: false
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# CHECK: selected: true
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registers:
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- { id: 0, class: gprb }
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- { id: 1, class: gprb }
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- { id: 2, class: gprb }
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body: |
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bb.0:
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liveins: %r0, %r1
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%0(s32) = COPY %r0
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; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
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%1(s32) = COPY %r1
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; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
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%2(s32) = G_XOR %0, %1
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; CHECK: [[VREGRES:%[0-9]+]]:gpr = EORrr [[VREGX]], [[VREGY]], 14, _
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%r0 = COPY %2(s32)
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; CHECK: %r0 = COPY [[VREGRES]]
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BX_RET 14, _, implicit %r0
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; CHECK: BX_RET 14, _, implicit %r0
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...
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---
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name: test_lshr_s32
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# CHECK-LABEL: name: test_lshr_s32
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legalized: true
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