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v4, v5 does not support sxtb / sxth. 

llvm-svn: 80322
This commit is contained in:
Evan Cheng 2009-08-28 00:31:43 +00:00
parent 108f2f6aa7
commit 6da267de23
3 changed files with 69 additions and 32 deletions
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12
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -701,13 +701,19 @@ def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
// If it's possible to use [r,r] address mode for sextload, select to
// If it's impossible to use [r,r] address mode for sextload, select to
// ldr{b|h} + sxt{b|h} instead.
def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
(tSXTB (tLDRB t_addrmode_s1:$addr))>;
(tSXTB (tLDRB t_addrmode_s1:$addr))>,
Requires<[IsThumb1Only, HasV6]>;
def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
(tSXTH (tLDRH t_addrmode_s2:$addr))>;
(tSXTH (tLDRH t_addrmode_s2:$addr))>,
Requires<[IsThumb1Only, HasV6]>;
def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
(tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
(tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
// Large immediate handling.

31
llvm/test/CodeGen/ARM/ldr_ext.ll
View File

@ -1,27 +1,36 @@
; RUN: llvm-as < %s | llc -march=arm | grep ldrb | count 1
; RUN: llvm-as < %s | llc -march=arm | grep ldrh | count 1
; RUN: llvm-as < %s | llc -march=arm | grep ldrsb | count 1
; RUN: llvm-as < %s | llc -march=arm | grep ldrsh | count 1
; RUN: llvm-as < %s | llc -march=arm | FileCheck %s
define i32 @test1(i8* %v.pntr.s0.u1) {
%tmp.u = load i8* %v.pntr.s0.u1
define i32 @test1(i8* %t1) nounwind {
; CHECK: ldrb
%tmp.u = load i8* %t1
%tmp1.s = zext i8 %tmp.u to i32
ret i32 %tmp1.s
}
define i32 @test2(i16* %v.pntr.s0.u1) {
%tmp.u = load i16* %v.pntr.s0.u1
define i32 @test2(i16* %t1) nounwind {
; CHECK: ldrh
%tmp.u = load i16* %t1
%tmp1.s = zext i16 %tmp.u to i32
ret i32 %tmp1.s
}
define i32 @test3(i8* %v.pntr.s1.u0) {
%tmp.s = load i8* %v.pntr.s1.u0
define i32 @test3(i8* %t0) nounwind {
; CHECK: ldrsb
%tmp.s = load i8* %t0
%tmp1.s = sext i8 %tmp.s to i32
ret i32 %tmp1.s
}
define i32 @test4() {
define i32 @test4(i16* %t0) nounwind {
; CHECK: ldrsh
%tmp.s = load i16* %t0
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s
}
define i32 @test5() nounwind {
; CHECK: mov r0, #0
; CHECK: ldrsh
%tmp.s = load i16* null
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s

58
llvm/test/CodeGen/Thumb/ldr_ext.ll
View File

@ -1,34 +1,56 @@
; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s
; RUN: llvm-as < %s | llc -march=thumb | FileCheck %s -check-prefix=V5
; RUN: llvm-as < %s | llc -march=thumb -mattr=+v6 | FileCheck %s -check-prefix=V6
define i32 @test1(i8* %v.pntr.s0.u1) {
; CHECK: test1:
; CHECK: ldrb
%tmp.u = load i8* %v.pntr.s0.u1
; rdar://7176514
define i32 @test1(i8* %t1) nounwind {
; V5: ldrb
; V6: ldrb
%tmp.u = load i8* %t1
%tmp1.s = zext i8 %tmp.u to i32
ret i32 %tmp1.s
}
define i32 @test2(i16* %v.pntr.s0.u1) {
; CHECK: test2:
; CHECK: ldrh
%tmp.u = load i16* %v.pntr.s0.u1
define i32 @test2(i16* %t1) nounwind {
; V5: ldrh
; V6: ldrh
%tmp.u = load i16* %t1
%tmp1.s = zext i16 %tmp.u to i32
ret i32 %tmp1.s
}
define i32 @test3(i8* %v.pntr.s1.u0) {
; CHECK: test3:
; CHECK: ldrb
; CHECK: sxtb
%tmp.s = load i8* %v.pntr.s1.u0
define i32 @test3(i8* %t0) nounwind {
; V5: ldrb
; V5: lsls
; V5: asrs
; V6: ldrb
; V6: sxtb
%tmp.s = load i8* %t0
%tmp1.s = sext i8 %tmp.s to i32
ret i32 %tmp1.s
}
define i32 @test4() {
; CHECK: test4:
; CHECK: movs
; CHECK: ldrsh
define i32 @test4(i16* %t0) nounwind {
; V5: ldrh
; V5: lsls
; V5: asrs
; V6: ldrh
; V6: sxth
%tmp.s = load i16* %t0
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s
}
define i32 @test5() nounwind {
; V5: movs r0, #0
; V5: ldrsh
; V6: movs r0, #0
; V6: ldrsh
%tmp.s = load i16* null
%tmp1.s = sext i16 %tmp.s to i32
ret i32 %tmp1.s