From 6d87f28afd467df3370d43af37760ce9b3d1a179 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 10 Nov 2015 00:30:14 +0000 Subject: [PATCH] Remove unnecessary call to getAllocatableRegClass I'm not sure what the point of this was. I'm not sure why you would ever define an instruction that produces an unallocatable register class. No tests fail with this removed, and it seems like it should be a verifier error to define such an instruction. This was problematic for AMDGPU because it would make bad decisions by arbitrarily changing the register class when unsetting isAllocatable for VS_32/VS_64, which is currently set as a workaround to this problem. AMDGPU uses the VS_32/VS_64 register classes to represent operands which can use either VGPRs or SGPRs. When isAllocatable is unset for these, this would need to pick either the SGPR or VGPR class and insert either a copy we don't want, or an illegal copy we would need to deal with later. A semi-arbitrary register class ordering decision is made in tablegen, which resulted in always picking a VGPR class because it happens to have more registers than the SGPR register class. We really just want to use whatever register class the original register had. llvm-svn: 252565 --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 5ec10308dc28..5268da2ff4f0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -330,11 +330,15 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, // shrink VReg's register class within reason. For example, if VReg == GR32 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. if (II) { - const TargetRegisterClass *DstRC = nullptr; + const TargetRegisterClass *OpRC = nullptr; if (IIOpNum < II->getNumOperands()) - DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); - if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { - unsigned NewVReg = MRI->createVirtualRegister(DstRC); + OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); + + if (OpRC && !MRI->constrainRegClass(VReg, OpRC, MinRCSize)) { + assert(OpRC->isAllocatable() && + "Constraining an allocatable VReg produced an unallocatable class?"); + + unsigned NewVReg = MRI->createVirtualRegister(OpRC); BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); VReg = NewVReg;