forked from OSchip/llvm-project
[X86][SSE] Improve legal SHUFP and PSHUFD shuffle matching
Updated X86TargetLowering::isShuffleMaskLegal to match SHUFP masks with commuted inputs and PSHUFD masks that reference the second input. As part of this I've refactored isPSHUFDMask to work in a more general manner and allow it to match against either the first or second input vector. Differential Revision: http://reviews.llvm.org/D6287 llvm-svn: 222087
This commit is contained in:
Simon Pilgrim
parent
382338d988
commit
6d675f4e35
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@ -3859,14 +3859,23 @@ static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
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}
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/// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
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/// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
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/// the second operand.
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static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
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if (VT == MVT::v4f32 || VT == MVT::v4i32 )
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return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
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if (VT == MVT::v2f64 || VT == MVT::v2i64)
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return (Mask[0] < 2 && Mask[1] < 2);
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return false;
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/// is suitable for input to PSHUFD. That is, it doesn't reference the other
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/// operand - by default will match for first operand.
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static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
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bool TestSecondOperand = false) {
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if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
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VT != MVT::v2f64 && VT != MVT::v2i64)
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return false;
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unsigned NumElems = VT.getVectorNumElements();
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unsigned Lo = TestSecondOperand ? NumElems : 0;
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unsigned Hi = Lo + NumElems;
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for (unsigned i = 0; i < NumElems; ++i)
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if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
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return false;
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return true;
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}
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/// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
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@ -19638,7 +19647,9 @@ X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
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isMOVLMask(M, SVT) ||
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isMOVHLPSMask(M, SVT) ||
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isSHUFPMask(M, SVT) ||
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isSHUFPMask(M, SVT, /* Commuted */ true) ||
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isPSHUFDMask(M, SVT) ||
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isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
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isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
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isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
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isPALIGNRMask(M, SVT, Subtarget) ||
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@ -614,22 +614,15 @@ define <4 x i64> @stress_test1(<4 x i64> %a, <4 x i64> %b) {
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; AVX1-NEXT: vperm2f128 {{.*#+}} ymm0 = ymm1[2,3,0,1]
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; AVX1-NEXT: vpermilpd {{.*#+}} ymm2 = ymm0[1,0,3,2]
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; AVX1-NEXT: vblendpd {{.*#+}} ymm1 = ymm2[0],ymm1[1],ymm2[2,3]
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
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; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
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; AVX1-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,3,2]
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; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
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; AVX1-NEXT: vpermilpd {{.*#+}} xmm1 = xmm1[1,0]
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: vunpckhpd {{.*#+}} ymm0 = ymm0[1],ymm1[1],ymm0[3],ymm1[3]
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: stress_test1:
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; AVX2: # BB#0:
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm1[3,1,1,0]
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,1,2,3]
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; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[3,3,1,3]
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; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
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; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,1,1,0]
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; AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3,4,5,6,7]
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; AVX2-NEXT: vpunpckhqdq {{.*#+}} ymm0 = ymm1[1],ymm0[1],ymm1[3],ymm0[3]
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; AVX2-NEXT: retq
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%c = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> <i32 3, i32 1, i32 1, i32 0>
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%d = shufflevector <4 x i64> %c, <4 x i64> undef, <4 x i32> <i32 3, i32 undef, i32 2, i32 undef>
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@ -1121,12 +1121,7 @@ define <4 x i32> @combine_nested_undef_test28(<4 x i32> %A, <4 x i32> %B) {
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define <4 x float> @combine_test1(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_test1:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps %xmm1, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_test1:
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@ -1248,12 +1243,7 @@ define <4 x float> @combine_test5(<4 x float> %a, <4 x float> %b) {
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define <4 x i32> @combine_test6(<4 x i32> %a, <4 x i32> %b) {
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; SSE2-LABEL: combine_test6:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps %xmm1, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm1[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_test6:
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@ -1601,21 +1591,13 @@ define <4 x i32> @combine_test20(<4 x i32> %a, <4 x i32> %b) {
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define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_test1b:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps %xmm1, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_test1b:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movaps %xmm1, %xmm2
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,2,0]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -1637,36 +1619,25 @@ define <4 x float> @combine_test1b(<4 x float> %a, <4 x float> %b) {
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define <4 x float> @combine_test2b(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_test2b:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps %xmm1, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: movaps %xmm2, %xmm0
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; SSE2-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0,0]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_test2b:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movaps %xmm1, %xmm2
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSSE3-NEXT: movaps %xmm2, %xmm0
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; SSSE3-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
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; SSSE3-NEXT: movapd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_test2b:
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; SSE41: # BB#0:
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; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
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; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; SSE41-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
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; SSE41-NEXT: movapd %xmm1, %xmm0
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; SSE41-NEXT: retq
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;
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; AVX-LABEL: combine_test2b:
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; AVX: # BB#0:
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; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]
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; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,1,3]
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; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0,0]
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; AVX-NEXT: retq
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%1 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 3>
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%2 = shufflevector <4 x float> %1, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 0, i32 5>
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@ -1698,21 +1669,13 @@ define <4 x float> @combine_test3b(<4 x float> %a, <4 x float> %b) {
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define <4 x float> @combine_test4b(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_test4b:
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; SSE2: # BB#0:
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; SSE2-NEXT: movaps %xmm1, %xmm2
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_test4b:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movaps %xmm1, %xmm2
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm0[1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]
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; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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@ -1968,17 +1931,11 @@ define <4 x float> @combine_blend_01(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_blend_01:
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; SSE2: # BB#0:
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; SSE2-NEXT: movsd %xmm1, %xmm0
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_blend_01:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: movsd %xmm1, %xmm0
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,3]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_blend_01:
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@ -2113,16 +2070,12 @@ define <4 x i32> @combine_test_movhl_3(<4 x i32> %a, <4 x i32> %b) {
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define <4 x float> @combine_undef_input_test1(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_undef_input_test1:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movsd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_undef_input_test1:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: movsd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_undef_input_test1:
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@ -2302,16 +2255,12 @@ define <4 x float> @combine_undef_input_test10(<4 x float> %a) {
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define <4 x float> @combine_undef_input_test11(<4 x float> %a, <4 x float> %b) {
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; SSE2-LABEL: combine_undef_input_test11:
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; SSE2: # BB#0:
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; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
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; SSE2-NEXT: movaps %xmm1, %xmm0
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; SSE2-NEXT: movsd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: combine_undef_input_test11:
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; SSSE3: # BB#0:
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; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,3,1]
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; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[1,2]
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; SSSE3-NEXT: movaps %xmm1, %xmm0
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; SSSE3-NEXT: movsd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: combine_undef_input_test11:
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