forked from OSchip/llvm-project
AMDGPU: Use conditions directly in division expansion
This was creating a select on true/false values, and then comparing that later. This produced more work for later combines, which can be avoided by just using the boolean values. This was copied from the original DAG expansion, which also has the same problem. This doesn't have a observable change using SelectionDAG, but since GlobalISel is missing these optimizations, the final code was noticeably longer.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
a5153dbc36
commit
6d4ebada79
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@ -987,7 +987,6 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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ConstantInt *Zero = Builder.getInt32(0);
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ConstantInt *One = Builder.getInt32(1);
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ConstantInt *MinusOne = Builder.getInt32(~0);
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Value *Sign = nullptr;
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if (IsSigned) {
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@ -1048,18 +1047,14 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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// Remainder = Num - Num_S_Remainder
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Value *Remainder = Builder.CreateSub(Num, Num_S_Remainder);
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// Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
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Value *Rem_GE_Den_CC = Builder.CreateICmpUGE(Remainder, Den);
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Value *Remainder_GE_Den = Builder.CreateSelect(Rem_GE_Den_CC, MinusOne, Zero);
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// Remainder_GE_Den = Remainder >= Den;
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Value *Remainder_GE_Den = Builder.CreateICmpUGE(Remainder, Den);
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// Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
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Value *Num_GE_Num_S_Rem_CC = Builder.CreateICmpUGE(Num, Num_S_Remainder);
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Value *Remainder_GE_Zero = Builder.CreateSelect(Num_GE_Num_S_Rem_CC,
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MinusOne, Zero);
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// Remainder_GE_Zero = Num >= Num_S_Remainder
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Value *Remainder_GE_Zero = Builder.CreateICmpUGE(Num, Num_S_Remainder);
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// Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
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Value *Tmp1 = Builder.CreateAnd(Remainder_GE_Den, Remainder_GE_Zero);
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Value *Tmp1_0_CC = Builder.CreateICmpEQ(Tmp1, Zero);
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Value *Res;
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if (IsDiv) {
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@ -1069,11 +1064,11 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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// Quotient_S_One = Quotient - 1
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Value *Quotient_S_One = Builder.CreateSub(Quotient, One);
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// Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
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Value *Div = Builder.CreateSelect(Tmp1_0_CC, Quotient, Quotient_A_One);
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// Div = (Tmp1 ? Quotient_A_One : Quotient)
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Value *Div = Builder.CreateSelect(Tmp1, Quotient_A_One, Quotient);
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// Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
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Res = Builder.CreateSelect(Num_GE_Num_S_Rem_CC, Div, Quotient_S_One);
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// Div = (Remainder_GE_Zero ? Div : Quotient_S_One)
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Res = Builder.CreateSelect(Remainder_GE_Zero, Div, Quotient_S_One);
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} else {
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// Remainder_S_Den = Remainder - Den
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Value *Remainder_S_Den = Builder.CreateSub(Remainder, Den);
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@ -1081,11 +1076,11 @@ Value* AMDGPUCodeGenPrepare::expandDivRem32(IRBuilder<> &Builder,
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// Remainder_A_Den = Remainder + Den
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Value *Remainder_A_Den = Builder.CreateAdd(Remainder, Den);
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// Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
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Value *Rem = Builder.CreateSelect(Tmp1_0_CC, Remainder, Remainder_S_Den);
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// Rem = (Tmp1 ? Remainder_S_Den : Remainder)
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Value *Rem = Builder.CreateSelect(Tmp1, Remainder_S_Den, Remainder);
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// Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
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Res = Builder.CreateSelect(Num_GE_Num_S_Rem_CC, Rem, Remainder_A_Den);
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// Rem = (Remainder_GE_Zero ? Rem : Remainder_A_Den)
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Res = Builder.CreateSelect(Remainder_GE_Zero, Rem, Remainder_A_Den);
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}
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if (IsSigned) {
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@ -121,18 +121,15 @@ define i32 @select_sdiv_lhs_opaque_const0_i32(i1 %cond) {
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; IR-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
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; IR-NEXT: [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
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; IR-NEXT: [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0
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; IR-NEXT: [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0
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; IR-NEXT: [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]]
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; IR-NEXT: [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0
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; IR-NEXT: [[TMP40:%.*]] = add i32 [[TMP31]], 1
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; IR-NEXT: [[TMP41:%.*]] = sub i32 [[TMP31]], 1
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; IR-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]]
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; IR-NEXT: [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]]
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; IR-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]]
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; IR-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]]
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; IR-NEXT: ret i32 [[TMP45]]
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; IR-NEXT: [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]]
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; IR-NEXT: [[TMP37:%.*]] = add i32 [[TMP31]], 1
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; IR-NEXT: [[TMP38:%.*]] = sub i32 [[TMP31]], 1
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; IR-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]]
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; IR-NEXT: [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]]
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; IR-NEXT: [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]]
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; IR-NEXT: [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]]
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; IR-NEXT: ret i32 [[TMP42]]
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;
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; GCN-LABEL: select_sdiv_lhs_opaque_const0_i32:
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; GCN: ; %bb.0:
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@ -219,18 +216,15 @@ define i32 @select_sdiv_lhs_opaque_const1_i32(i1 %cond) {
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; IR-NEXT: [[TMP32:%.*]] = mul i32 [[TMP31]], [[TMP4]]
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; IR-NEXT: [[TMP33:%.*]] = sub i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP34:%.*]] = icmp uge i32 [[TMP33]], [[TMP4]]
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; IR-NEXT: [[TMP35:%.*]] = select i1 [[TMP34]], i32 -1, i32 0
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; IR-NEXT: [[TMP36:%.*]] = icmp uge i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP37:%.*]] = select i1 [[TMP36]], i32 -1, i32 0
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; IR-NEXT: [[TMP38:%.*]] = and i32 [[TMP35]], [[TMP37]]
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; IR-NEXT: [[TMP39:%.*]] = icmp eq i32 [[TMP38]], 0
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; IR-NEXT: [[TMP40:%.*]] = add i32 [[TMP31]], 1
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; IR-NEXT: [[TMP41:%.*]] = sub i32 [[TMP31]], 1
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; IR-NEXT: [[TMP42:%.*]] = select i1 [[TMP39]], i32 [[TMP31]], i32 [[TMP40]]
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; IR-NEXT: [[TMP43:%.*]] = select i1 [[TMP36]], i32 [[TMP42]], i32 [[TMP41]]
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; IR-NEXT: [[TMP44:%.*]] = xor i32 [[TMP43]], [[TMP2]]
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; IR-NEXT: [[TMP45:%.*]] = sub i32 [[TMP44]], [[TMP2]]
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; IR-NEXT: ret i32 [[TMP45]]
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; IR-NEXT: [[TMP35:%.*]] = icmp uge i32 1000000, [[TMP32]]
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; IR-NEXT: [[TMP36:%.*]] = and i1 [[TMP34]], [[TMP35]]
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; IR-NEXT: [[TMP37:%.*]] = add i32 [[TMP31]], 1
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; IR-NEXT: [[TMP38:%.*]] = sub i32 [[TMP31]], 1
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; IR-NEXT: [[TMP39:%.*]] = select i1 [[TMP36]], i32 [[TMP37]], i32 [[TMP31]]
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; IR-NEXT: [[TMP40:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP38]]
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; IR-NEXT: [[TMP41:%.*]] = xor i32 [[TMP40]], [[TMP2]]
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; IR-NEXT: [[TMP42:%.*]] = sub i32 [[TMP41]], [[TMP2]]
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; IR-NEXT: ret i32 [[TMP42]]
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;
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; GCN-LABEL: select_sdiv_lhs_opaque_const1_i32:
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; GCN: ; %bb.0:
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