forked from OSchip/llvm-project
rdar://problem/11541676
Do not show the derived registers like "eax", ... for the vanilla "register read" command. Also add a test scenario for that. llvm-svn: 157647
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@ -124,7 +124,8 @@ public:
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DumpRegisterSet (const ExecutionContext &exe_ctx,
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Stream &strm,
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RegisterContext *reg_ctx,
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uint32_t set_idx)
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uint32_t set_idx,
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bool primitive_only=false)
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{
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uint32_t unavailable_count = 0;
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uint32_t available_count = 0;
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@ -137,7 +138,11 @@ public:
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for (uint32_t reg_idx = 0; reg_idx < num_registers; ++reg_idx)
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{
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const uint32_t reg = reg_set->registers[reg_idx];
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if (DumpRegister (exe_ctx, strm, reg_ctx, reg_ctx->GetRegisterInfoAtIndex(reg)))
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const RegisterInfo *reg_info = reg_ctx->GetRegisterInfoAtIndex(reg);
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// Skip the dumping of derived register if primitive_only is true.
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if (primitive_only && reg_info && reg_info->value_regs)
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continue;
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if (DumpRegister (exe_ctx, strm, reg_ctx, reg_info))
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++available_count;
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else
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++unavailable_count;
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@ -202,7 +207,8 @@ public:
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for (set_idx = 0; set_idx < num_register_sets; ++set_idx)
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{
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DumpRegisterSet (exe_ctx, strm, reg_ctx, set_idx);
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// When dump_all_sets option is set, dump primitive as well as derived registers.
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DumpRegisterSet (exe_ctx, strm, reg_ctx, set_idx, !m_command_options.dump_all_sets.GetCurrentValue());
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}
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}
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}
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@ -71,6 +71,13 @@ class RegisterCommandsTestCase(TestBase):
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self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
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substrs = ['stopped', 'stop reason = breakpoint'])
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# The vanilla "register read" command does not output derived register like eax.
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self.expect("register read", matching=False,
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substrs = ['eax'])
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# While "register read -a" does output derived register like eax.
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self.expect("register read -a", matching=True,
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substrs = ['eax'])
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# Test reading of rax and eax.
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self.runCmd("register read rax eax")
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