forked from OSchip/llvm-project
[CodeGenPrepare] Delete intrinsic call to llvm.assume to enable more tailcall
The attached test case is simplified from tcmalloc. Both function calls should be optimized as tailcall. But llvm can only optimize the first call. The second call can't be optimized because function dupRetToEnableTailCallOpts failed to duplicate ret into block case2. There 2 problems blocked the duplication: 1 Intrinsic call llvm.assume is not handled by dupRetToEnableTailCallOpts. 2 The control flow is more complex than expected, dupRetToEnableTailCallOpts can only duplicate ret into its predecessor, but here we have an intermediate block between call and ret. The solutions: 1 Since CodeGenPrepare is already at the end of LLVM IR phase, we can simply delete the intrinsic call to llvm.assume. 2 A general solution to the complex control flow is hard, but for this case, after exit2 is duplicated into case1, exit2 is the only successor of exit1 and exit1 is the only predecessor of exit2, so they can be combined through eliminateFallThrough. But this function is called too late, there is no more dupRetToEnableTailCallOpts after it. We can add an earlier call to eliminateFallThrough to solve it. Differential Revision: https://reviews.llvm.org/D76539
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@ -495,6 +495,9 @@ bool CodeGenPrepare::runOnFunction(Function &F) {
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if (!LargeOffsetGEPMap.empty())
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MadeChange |= splitLargeGEPOffsets();
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if (MadeChange)
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eliminateFallThrough(F);
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// Really free removed instructions during promotion.
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for (Instruction *I : RemovedInsts)
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I->deleteValue();
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@ -1964,6 +1967,11 @@ bool CodeGenPrepare::optimizeCallInst(CallInst *CI, bool &ModifiedDT) {
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if (II) {
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switch (II->getIntrinsicID()) {
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default: break;
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case Intrinsic::assume: {
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II->eraseFromParent();
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return true;
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}
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case Intrinsic::experimental_widenable_condition: {
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// Give up on future widening oppurtunties so that we can fold away dead
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// paths and merge blocks before going into block-local instruction
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@ -13,7 +13,6 @@ block1:
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%s1 = sext i64 %l1 to i128
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br label %block2
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; CHECK-LABEL: block2:
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; CHECK-NEXT: sext
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; CHECK-NEXT: load
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; CHECK-NEXT: sext
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@ -34,7 +33,6 @@ block1:
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%l1 = load i32, i32* %mem1
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br label %block2
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; CHECK-LABEL: block2:
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; CHECK-NEXT: load
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; CHECK-NEXT: sext
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block2:
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@ -15,9 +15,10 @@ define i1 @PR41004(i32 %x, i32 %y, i32 %t1) {
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; CHECK-NEXT: br label [[SELECT_END]]
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; CHECK: select.end:
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; CHECK-NEXT: [[MUL:%.*]] = phi i32 [ [[REM]], [[SELECT_TRUE_SINK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[NEG:%.*]] = add i32 [[T1:%.*]], -1
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; CHECK-NEXT: [[USUB:%.*]] = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 [[T1:%.*]], i32 1)
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; CHECK-NEXT: [[NEG:%.*]] = extractvalue { i32, i1 } [[USUB]], 0
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; CHECK-NEXT: [[TOBOOL:%.*]] = extractvalue { i32, i1 } [[USUB]], 1
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[NEG]], [[MUL]]
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; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[T1]], 0
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; CHECK-NEXT: ret i1 [[TOBOOL]]
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;
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entry:
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@ -0,0 +1,48 @@
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; RUN: opt -codegenprepare -S -mtriple=x86_64-linux < %s | FileCheck %s
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; The ret instruction can be duplicated into BB case2 even though there is an
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; intermediate BB exit1 and call to llvm.assume.
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@ptr = external global i8*, align 8
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; CHECK: %ret1 = tail call i8* @qux()
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; CHECK-NEXT: ret i8* %ret1
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; CHECK: %ret2 = tail call i8* @bar()
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; CHECK-NEXT: ret i8* %ret2
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define i8* @foo(i64 %size, i64 %v1, i64 %v2) {
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entry:
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%cmp1 = icmp ult i64 %size, 1025
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br i1 %cmp1, label %if.end, label %case1
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case1:
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%ret1 = tail call i8* @qux()
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br label %exit2
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if.end:
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%cmp2 = icmp ult i64 %v1, %v2
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br i1 %cmp2, label %case3, label %case2
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case2:
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%ret2 = tail call i8* @bar()
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br label %exit1
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case3:
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%ret3 = load i8*, i8** @ptr, align 8
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br label %exit1
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exit1:
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%retval1 = phi i8* [ %ret2, %case2 ], [ %ret3, %case3 ]
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%cmp3 = icmp ne i8* %retval1, null
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tail call void @llvm.assume(i1 %cmp3)
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br label %exit2
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exit2:
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%retval2 = phi i8* [ %ret1, %case1 ], [ %retval1, %exit1 ]
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ret i8* %retval2
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}
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declare void @llvm.assume(i1)
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declare i8* @qux()
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declare i8* @bar()
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