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Reorganize and simplify local variables. 

llvm-svn: 213809
This commit is contained in:
Eric Christopher 2014-07-23 22:27:10 +00:00
parent 5addace56d
commit 6d0e40bfbf
1 changed files with 11 additions and 13 deletions
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24
llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
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@ -40,19 +40,17 @@ static cl::opt<signed> RegPressureThreshold(
"dfa-sched-reg-pressure-threshold", cl::Hidden, cl::ZeroOrMore, cl::init(5),
cl::desc("Track reg pressure and switch priority to in-depth"));
ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS) :
Picker(this),
InstrItins(IS->getTargetLowering()->getTargetMachine().getInstrItineraryData())
{
TII = IS->getTargetLowering()->getTargetMachine().getInstrInfo();
TRI = IS->getTargetLowering()->getTargetMachine().getRegisterInfo();
TLI = IS->getTargetLowering();
const TargetMachine &tm = (*IS->MF).getTarget();
ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,nullptr);
// This hard requirement could be relaxed, but for now
// do not let it procede.
ResourcePriorityQueue::ResourcePriorityQueue(SelectionDAGISel *IS)
: Picker(this),
InstrItins(
IS->getTargetLowering()->getTargetMachine().getInstrItineraryData()) {
const TargetMachine &TM = (*IS->MF).getTarget();
TRI = TM.getRegisterInfo();
TLI = IS->getTargetLowering();
TII = TM.getInstrInfo();
ResourcesModel = TII->CreateTargetScheduleState(&TM, nullptr);
// This hard requirement could be relaxed, but for now
// do not let it procede.
assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
unsigned NumRC = TRI->getNumRegClasses();