From 6cfc9ba5e3ea2dba7c0bbb2e26dc6653568c7d8e Mon Sep 17 00:00:00 2001 From: Simon Dardis Date: Wed, 2 May 2018 09:55:49 +0000 Subject: [PATCH] [mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341 --- llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 12 +++--- llvm/lib/Target/Mips/MipsInstrInfo.td | 30 +++++++------- llvm/test/MC/Mips/micromips/valid.s | 6 +++ llvm/test/MC/Mips/mips1/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips2/valid.s | 33 ++++++++++++++- llvm/test/MC/Mips/mips3/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips32/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips32r2/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips32r3/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips32r5/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips32r6/valid.s | 48 ++++++++++++++++++++-- llvm/test/MC/Mips/mips4/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips5/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips64/valid.s | 30 ++++++++++++++ llvm/test/MC/Mips/mips64r2/valid.s | 34 ++++++++++++++- llvm/test/MC/Mips/mips64r3/valid.s | 33 +++++++++++++++ llvm/test/MC/Mips/mips64r5/valid.s | 34 ++++++++++++++- llvm/test/MC/Mips/mips64r6/valid.s | 48 ++++++++++++++++++++-- 18 files changed, 515 insertions(+), 33 deletions(-) diff --git a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index 4186dd7969b8..72513534a185 100644 --- a/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -769,17 +769,17 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Shift Instructions def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>, - SRA_FM_MM<0, 0>; + SRA_FM_MM<0, 0>, ISA_MICROMIPS; def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>, - SRA_FM_MM<0x40, 0>; + SRA_FM_MM<0x40, 0>, ISA_MICROMIPS; def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>, - SRA_FM_MM<0x80, 0>; + SRA_FM_MM<0x80, 0>, ISA_MICROMIPS; def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>, - SRLV_FM_MM<0x10, 0>; + SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS; def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>, - SRLV_FM_MM<0x50, 0>; + SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS; def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>, - SRLV_FM_MM<0x90, 0>; + SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS; def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>, SRA_FM_MM<0xc0, 0> { list Pattern = [(set GPR32Opnd:$rd, diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 20e6fddbb8ae..5189c0dec714 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -2010,24 +2010,22 @@ let AdditionalPredicates = [NotInMicroMips] in { def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; } -/// Shift Instructions let AdditionalPredicates = [NotInMicroMips] in { -def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, - immZExt5>, SRA_FM<0, 0>; -def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, - immZExt5>, SRA_FM<2, 0>; -def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, - immZExt5>, SRA_FM<3, 0>; -def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, - SRLV_FM<4, 0>; -def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, - SRLV_FM<6, 0>; -def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, - SRLV_FM<7, 0>; -} + /// Shift Instructions + def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, + immZExt5>, SRA_FM<0, 0>, ISA_MIPS1; + def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, + immZExt5>, SRA_FM<2, 0>, ISA_MIPS1; + def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, + immZExt5>, SRA_FM<3, 0>, ISA_MIPS1; + def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, + SRLV_FM<4, 0>, ISA_MIPS1; + def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>, + SRLV_FM<6, 0>, ISA_MIPS1; + def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>, + SRLV_FM<7, 0>, ISA_MIPS1; -// Rotate Instructions -let AdditionalPredicates = [NotInMicroMips] in { + // Rotate Instructions def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr, immZExt5>, SRA_FM<2, 1>, ISA_MIPS32R2; diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index 974229d0deb1..d246c51c8f85 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -97,11 +97,17 @@ div.d $f0, $f2, $f4 # CHECK: div.d $f0, $f2, $f4 # encoding: [0x54,0x # CHECK-NEXT: #