maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

make gep matching in fastisel match the base of the gep as a 

register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.

llvm-svn: 97739
This commit is contained in:
Chris Lattner 2010-03-04 19:48:19 +00:00
parent c1cb75eb72
commit 6ce8e24b70
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -425,10 +425,17 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
break;
// Ok, the GEP indices were covered by constant-offset and scaled-index
// addressing. Update the address state and move on to examining the base.
X86AddressMode SavedAM = AM;
AM.IndexReg = IndexReg;
AM.Scale = Scale;
AM.Disp = (uint32_t)Disp;
return X86SelectAddress(U->getOperand(0), AM);
if (X86SelectAddress(U->getOperand(0), AM))
return true;
// If we couldn't merge the sub value into this addr mode, revert back to
// our address and just match the value instead of completely failing.
AM = SavedAM;
break;
unsupported_gep:
// Ok, the GEP indices weren't all covered.
break;