From 6ce8e24b7061cda389001c3de151015bf9051ab3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Thu, 4 Mar 2010 19:48:19 +0000 Subject: [PATCH] make gep matching in fastisel match the base of the gep as a register if it isn't possible to match the indexes *and* the base. This fixes some fast isel rejects of load instructions on oggenc. llvm-svn: 97739 --- llvm/lib/Target/X86/X86FastISel.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 17366ee8bcb4..c6da5cc437db 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -425,10 +425,17 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { break; // Ok, the GEP indices were covered by constant-offset and scaled-index // addressing. Update the address state and move on to examining the base. + X86AddressMode SavedAM = AM; AM.IndexReg = IndexReg; AM.Scale = Scale; AM.Disp = (uint32_t)Disp; - return X86SelectAddress(U->getOperand(0), AM); + if (X86SelectAddress(U->getOperand(0), AM)) + return true; + + // If we couldn't merge the sub value into this addr mode, revert back to + // our address and just match the value instead of completely failing. + AM = SavedAM; + break; unsupported_gep: // Ok, the GEP indices weren't all covered. break;