From 6ccbd16433dc535333479ec71cca2c1da55b2976 Mon Sep 17 00:00:00 2001
From: Stefan Maksimovic <stefan.maksimovic@mips.com>
Date: Wed, 22 Aug 2018 09:34:44 +0000
Subject: [PATCH] [mips] Handle missing CondCodes

Add patterns for unhandled CondCode enumerables:
SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE.

Stated at the ISD::CondCode enum declaration:
`All of these (except for the 'always folded ops')
should be handled for floating point.`

Add patterns which use these nodes, same as corresponding
'ordered' CondCode nodes.

Referring to 'Ordered means that neither operand is a QNAN'
we assume it is safe to match ex. SETLT node to the same
instruction as SETOLT.

Differential Revision: https://reviews.llvm.org/D50757

llvm-svn: 340392
---
 llvm/lib/Target/Mips/MipsMSAInstrInfo.td     | 29 +++++++++
 llvm/test/CodeGen/Mips/msa/cc_without_nan.ll | 63 ++++++++++++++++++++
 2 files changed, 92 insertions(+)
 create mode 100644 llvm/test/CodeGen/Mips/msa/cc_without_nan.ll

diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index d83f75ffa1c1..eecc7c573df1 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -107,6 +107,18 @@ class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
           (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
 
 // ISD::SETFALSE cannot occur
+def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>;
+def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>;
+def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>;
+def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>;
+def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>;
+def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>;
+def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>;
+def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>;
+def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>;
+def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>;
+def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>;
+def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>;
 def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
 def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
@@ -4038,3 +4050,20 @@ def : MSAPat<
          (SPLAT_D v2f64:$ws,
            (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
          sub_64))>;
+
+def : MSAPat<(vfseteq_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCEQ_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfseteq_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCEQ_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetle_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCLE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetle_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCLE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetlt_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCLT_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetlt_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCLT_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
+def : MSAPat<(vfsetne_v4f32 MSA128WOpnd:$a, MSA128WOpnd:$b),
+             (FCNE_W MSA128WOpnd:$a, MSA128WOpnd:$b)>;
+def : MSAPat<(vfsetne_v2f64 MSA128DOpnd:$a, MSA128DOpnd:$b),
+             (FCNE_D MSA128DOpnd:$a, MSA128DOpnd:$b)>;
diff --git a/llvm/test/CodeGen/Mips/msa/cc_without_nan.ll b/llvm/test/CodeGen/Mips/msa/cc_without_nan.ll
new file mode 100644
index 000000000000..835a7cfcce4f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/msa/cc_without_nan.ll
@@ -0,0 +1,63 @@
+; RUN: llc -mtriple mips64-unknown-linux -mcpu=mips64r5 -mattr=+msa < %s | FileCheck %s
+
+; The fcmp fast flag will result in conversion from
+; setolt, setoeq, setole, setone to
+; setlt, seteq, setle, setne nodes.
+; Test that the latter nodes are matched to the same instructions as the former.
+
+define <2 x i1> @testlt_v2f64(<2 x double> %a, <2 x double> %b) {
+start:
+  %0 = fcmp fast olt <2 x double> %a, %b
+  ; CHECK: fclt.d
+  ret <2 x i1> %0
+}
+
+define <4 x i1>  @testlt_v4f32(<4 x float> %a, <4 x float> %b) {
+start:
+  %0 = fcmp fast olt <4 x float> %a, %b
+  ; CHECK: fclt.w
+  ret <4 x i1> %0
+}
+
+define <2 x i1> @testeq_v2f64(<2 x double> %a, <2 x double> %b) {
+start:
+  %0 = fcmp fast oeq <2 x double> %a, %b
+  ; CHECK: fceq.d
+  ret <2 x i1> %0
+}
+
+define <4 x i1> @testeq_v4f32(<4 x float> %a, <4 x float> %b) {
+start:
+  %0 = fcmp fast oeq <4 x float> %a, %b
+  ; CHECK: fceq.w
+  ret <4 x i1> %0
+}
+
+define <2 x i1> @testle_v2f64(<2 x double> %a, <2 x double> %b) {
+start:
+  %0 = fcmp fast ole <2 x double> %a, %b
+  ; CHECK: fcle.d
+  ret <2 x i1> %0
+}
+
+define <4 x i1> @testle_v4f32(<4 x float> %a, <4 x float> %b) {
+start:
+  %0 = fcmp fast ole <4 x float> %a, %b
+  ; CHECK: fcle.w
+  ret <4 x i1> %0
+}
+
+define <2 x i1> @testne_v2f64(<2 x double> %a, <2 x double> %b) {
+start:
+  %0 = fcmp fast one <2 x double> %a, %b
+  ; CHECK: fcne.d
+  ret <2 x i1> %0
+}
+
+define <4 x i1> @testne_v4f32(<4 x float> %a, <4 x float> %b) {
+start:
+  %0 = fcmp fast one <4 x float> %a, %b
+  ; CHECK: fcne.w
+  ret <4 x i1> %0
+}
+