forked from OSchip/llvm-project
AArch64/GlobalISel: Narrow stack passed argument access size
This fixes a verifier error in the testcase from bug 47619.
The stack passed s3 value was widened to 4-bytes, and producing a
4-byte memory access with a < 1 byte result type. We need to either
widen the result type or narrow the access size. This copies the code
directly from the AMDGPU handling, which narrows the load size. I
don't like that every target has to handle this, but this is currently
broken on the 11 release branch and this is the simplest fix.
This reverts commit 42bfa7c63b
.
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@ -84,11 +84,16 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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}
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}
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void assignValueToAddress(Register ValVReg, Register Addr, uint64_t Size,
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void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
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MachinePointerInfo &MPO, CCValAssign &VA) override {
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MachineFunction &MF = MIRBuilder.getMF();
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// The reported memory location may be wider than the value.
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const LLT RegTy = MRI.getType(ValVReg);
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MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize);
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auto MMO = MF.getMachineMemOperand(
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, Size,
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemSize,
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inferAlignFromPtrInfo(MF, MPO));
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MIRBuilder.buildLoad(ValVReg, Addr, *MMO);
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}
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@ -0,0 +1,26 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -mtriple=aarch64-unknown-unknown -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
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; Make sure the i3 %arg8 value is correctly handled. This was trying
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; to use MVT for EVT values passed on the stack and asserting before
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; b98f902f1877c3d679f77645a267edc89ffcd5d6
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define i3 @bug47619(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i3 %arg8) {
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; CHECK-LABEL: name: bug47619
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; CHECK: bb.1.bb:
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; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD:%[0-9]+]]:_(s3) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.0, align 16)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s3)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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bb:
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ret i3 %arg8
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}
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