forked from OSchip/llvm-project
[InstCombine] add tests for icmp with extended operands; NFC
This commit is contained in:
Sanjay Patel
parent
6631907ad2
commit
6c8cb219f5
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@ -1,20 +0,0 @@
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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; PR1940
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define i1 @test1(i8 %A, i8 %B) {
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%a = zext i8 %A to i32
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%b = zext i8 %B to i32
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%c = icmp sgt i32 %a, %b
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ret i1 %c
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; CHECK: %c = icmp ugt i8 %A, %B
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; CHECK: ret i1 %c
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}
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define i1 @test2(i8 %A, i8 %B) {
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%a = sext i8 %A to i32
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%b = sext i8 %B to i32
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%c = icmp ugt i32 %a, %b
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ret i1 %c
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; CHECK: %c = icmp ugt i8 %A, %B
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; CHECK: ret i1 %c
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}
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@ -0,0 +1,398 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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; PR1940
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define i1 @zext_zext_sgt(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_zext_sgt(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = zext i8 %y to i32
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%c = icmp sgt i32 %a, %b
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ret i1 %c
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}
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define <2 x i1> @zext_zext_ugt(<2 x i8> %x, <2 x i8> %y) {
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; CHECK-LABEL: @zext_zext_ugt(
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; CHECK-NEXT: [[C:%.*]] = icmp ugt <2 x i8> [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%a = zext <2 x i8> %x to <2 x i32>
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%b = zext <2 x i8> %y to <2 x i32>
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%c = icmp ugt <2 x i32> %a, %b
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ret <2 x i1> %c
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}
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define i1 @zext_zext_eq(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_zext_eq(
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; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = zext i8 %y to i32
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%c = icmp eq i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_zext_sle_op0_narrow(i8 %x, i16 %y) {
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; CHECK-LABEL: @zext_zext_sle_op0_narrow(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[X:%.*]] to i16
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; CHECK-NEXT: [[C:%.*]] = icmp ule i16 [[TMP1]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = zext i16 %y to i32
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%c = icmp sle i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_zext_ule_op0_wide(i9 %x, i8 %y) {
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; CHECK-LABEL: @zext_zext_ule_op0_wide(
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; CHECK-NEXT: [[TMP1:%.*]] = zext i8 [[Y:%.*]] to i9
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; CHECK-NEXT: [[C:%.*]] = icmp uge i9 [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i9 %x to i32
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%b = zext i8 %y to i32
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%c = icmp ule i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_sext_slt(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_sext_slt(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp slt i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_sext_ult(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_sext_ult(
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; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp ult i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_sext_ne(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_sext_ne(
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; CHECK-NEXT: [[C:%.*]] = icmp ne i8 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp ne i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_sext_sge_op0_narrow(i5 %x, i8 %y) {
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; CHECK-LABEL: @sext_sext_sge_op0_narrow(
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; CHECK-NEXT: [[TMP1:%.*]] = sext i5 [[X:%.*]] to i8
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; CHECK-NEXT: [[C:%.*]] = icmp sge i8 [[TMP1]], [[Y:%.*]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i5 %x to i32
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%b = sext i8 %y to i32
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%c = icmp sge i32 %a, %b
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ret i1 %c
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}
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define <2 x i1> @sext_sext_uge_op0_wide(<2 x i16> %x, <2 x i8> %y) {
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; CHECK-LABEL: @sext_sext_uge_op0_wide(
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; CHECK-NEXT: [[TMP1:%.*]] = sext <2 x i8> [[Y:%.*]] to <2 x i16>
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; CHECK-NEXT: [[C:%.*]] = icmp ule <2 x i16> [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%a = sext <2 x i16> %x to <2 x i32>
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%b = sext <2 x i8> %y to <2 x i32>
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%c = icmp uge <2 x i32> %a, %b
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ret <2 x i1> %c
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}
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define i1 @zext_sext_sgt(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_sgt(
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp sgt i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_ugt(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_ugt(
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp ugt i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_eq(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_eq(
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = sext i8 %y to i32
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%c = icmp eq i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_sle_op0_narrow(i8 %x, i16 %y) {
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; CHECK-LABEL: @zext_sext_sle_op0_narrow(
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i16 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp sle i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i8 %x to i32
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%b = sext i16 %y to i32
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%c = icmp sle i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_ule_op0_wide(i9 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_ule_op0_wide(
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; CHECK-NEXT: [[A:%.*]] = zext i9 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = zext i9 %x to i32
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%b = sext i8 %y to i32
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%c = icmp ule i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_zext_slt(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_slt(
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; CHECK-NEXT: [[A:%.*]] = sext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%b = zext i8 %y to i32
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%c = icmp slt i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_zext_ult(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_ult(
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; CHECK-NEXT: [[A:%.*]] = sext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%b = zext i8 %y to i32
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%c = icmp ult i32 %a, %b
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ret i1 %c
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}
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define <2 x i1> @sext_zext_ne(<2 x i8> %x, <2 x i8> %y) {
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; CHECK-LABEL: @sext_zext_ne(
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; CHECK-NEXT: [[A:%.*]] = sext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[B:%.*]] = zext <2 x i8> [[Y:%.*]] to <2 x i32>
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; CHECK-NEXT: [[C:%.*]] = icmp ne <2 x i32> [[A]], [[B]]
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%a = sext <2 x i8> %x to <2 x i32>
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%b = zext <2 x i8> %y to <2 x i32>
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%c = icmp ne <2 x i32> %a, %b
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ret <2 x i1> %c
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}
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define i1 @sext_zext_sge_op0_narrow(i5 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_sge_op0_narrow(
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; CHECK-NEXT: [[A:%.*]] = sext i5 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp sge i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i5 %x to i32
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%b = zext i8 %y to i32
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%c = icmp sge i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_zext_uge_op0_wide(i16 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_uge_op0_wide(
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; CHECK-NEXT: [[A:%.*]] = sext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i16 %x to i32
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%b = zext i8 %y to i32
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%c = icmp uge i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_sgt_known_nonneg(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_sgt_known_nonneg(
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; CHECK-NEXT: [[N:%.*]] = udiv i8 127, [[X:%.*]]
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%n = udiv i8 127, %x
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%a = zext i8 %n to i32
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%b = sext i8 %y to i32
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%c = icmp sgt i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_ugt_known_nonneg(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_ugt_known_nonneg(
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; CHECK-NEXT: [[N:%.*]] = and i8 [[X:%.*]], 127
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%n = and i8 %x, 127
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%a = zext i8 %n to i32
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%b = sext i8 %y to i32
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%c = icmp ugt i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_eq_known_nonneg(i8 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_eq_known_nonneg(
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; CHECK-NEXT: [[N:%.*]] = lshr i8 [[X:%.*]], 1
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%n = lshr i8 %x, 1
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%a = zext i8 %n to i32
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%b = sext i8 %y to i32
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%c = icmp eq i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_sle_known_nonneg_op0_narrow(i8 %x, i16 %y) {
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; CHECK-LABEL: @zext_sext_sle_known_nonneg_op0_narrow(
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; CHECK-NEXT: [[N:%.*]] = and i8 [[X:%.*]], 12
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; CHECK-NEXT: [[A:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i16 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp sle i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%n = and i8 %x, 12
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%a = zext i8 %n to i32
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%b = sext i16 %y to i32
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%c = icmp sle i32 %a, %b
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ret i1 %c
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}
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define i1 @zext_sext_ule_known_nonneg_op0_wide(i9 %x, i8 %y) {
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; CHECK-LABEL: @zext_sext_ule_known_nonneg_op0_wide(
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; CHECK-NEXT: [[N:%.*]] = urem i9 [[X:%.*]], 254
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; CHECK-NEXT: [[A:%.*]] = zext i9 [[N]] to i32
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; CHECK-NEXT: [[B:%.*]] = sext i8 [[Y:%.*]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ule i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%n = urem i9 %x, 254
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%a = zext i9 %n to i32
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%b = sext i8 %y to i32
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%c = icmp ule i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_zext_slt_known_nonneg(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_slt_known_nonneg(
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; CHECK-NEXT: [[A:%.*]] = sext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[N:%.*]] = and i8 [[Y:%.*]], 126
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
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%n = and i8 %y, 126
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%b = zext i8 %n to i32
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%c = icmp slt i32 %a, %b
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ret i1 %c
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}
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define i1 @sext_zext_ult_known_nonneg(i8 %x, i8 %y) {
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; CHECK-LABEL: @sext_zext_ult_known_nonneg(
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; CHECK-NEXT: [[A:%.*]] = sext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[N:%.*]] = lshr i8 [[Y:%.*]], 6
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; CHECK-NEXT: [[B:%.*]] = zext i8 [[N]] to i32
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[A]], [[B]]
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; CHECK-NEXT: ret i1 [[C]]
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;
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%a = sext i8 %x to i32
|
||||
%n = lshr i8 %y, 6
|
||||
%b = zext i8 %n to i32
|
||||
%c = icmp ult i32 %a, %b
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define i1 @sext_zext_ne_known_nonneg(i8 %x, i8 %y) {
|
||||
; CHECK-LABEL: @sext_zext_ne_known_nonneg(
|
||||
; CHECK-NEXT: [[A:%.*]] = sext i8 [[X:%.*]] to i32
|
||||
; CHECK-NEXT: [[N:%.*]] = udiv i8 [[Y:%.*]], 6
|
||||
; CHECK-NEXT: [[B:%.*]] = zext i8 [[N]] to i32
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp ne i32 [[A]], [[B]]
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%a = sext i8 %x to i32
|
||||
%n = udiv i8 %y, 6
|
||||
%b = zext i8 %n to i32
|
||||
%c = icmp ne i32 %a, %b
|
||||
ret i1 %c
|
||||
}
|
||||
|
||||
define <2 x i1> @sext_zext_sge_known_nonneg_op0_narrow(<2 x i5> %x, <2 x i8> %y) {
|
||||
; CHECK-LABEL: @sext_zext_sge_known_nonneg_op0_narrow(
|
||||
; CHECK-NEXT: [[A:%.*]] = sext <2 x i5> [[X:%.*]] to <2 x i32>
|
||||
; CHECK-NEXT: [[N:%.*]] = mul nsw <2 x i8> [[Y:%.*]], [[Y]]
|
||||
; CHECK-NEXT: [[B:%.*]] = zext <2 x i8> [[N]] to <2 x i32>
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp sge <2 x i32> [[A]], [[B]]
|
||||
; CHECK-NEXT: ret <2 x i1> [[C]]
|
||||
;
|
||||
%a = sext <2 x i5> %x to <2 x i32>
|
||||
%n = mul nsw <2 x i8> %y, %y
|
||||
%b = zext <2 x i8> %n to <2 x i32>
|
||||
%c = icmp sge <2 x i32> %a, %b
|
||||
ret <2 x i1> %c
|
||||
}
|
||||
|
||||
define i1 @sext_zext_uge_known_nonneg_op0_wide(i16 %x, i8 %y) {
|
||||
; CHECK-LABEL: @sext_zext_uge_known_nonneg_op0_wide(
|
||||
; CHECK-NEXT: [[A:%.*]] = sext i16 [[X:%.*]] to i32
|
||||
; CHECK-NEXT: [[N:%.*]] = and i8 [[Y:%.*]], 12
|
||||
; CHECK-NEXT: [[B:%.*]] = zext i8 [[N]] to i32
|
||||
; CHECK-NEXT: [[C:%.*]] = icmp uge i32 [[A]], [[B]]
|
||||
; CHECK-NEXT: ret i1 [[C]]
|
||||
;
|
||||
%a = sext i16 %x to i32
|
||||
%n = and i8 %y, 12
|
||||
%b = zext i8 %n to i32
|
||||
%c = icmp uge i32 %a, %b
|
||||
ret i1 %c
|
||||
}
|
||||
Loading…
Reference in New Issue