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[x86] add more tests for lowerShuffleWithUndefHalf; NFC 

Some other transform is creating the opposite form and causing 
an infinite loop if we try to split some of these.

llvm-svn: 352327
This commit is contained in:
Sanjay Patel 2019-01-27 20:17:02 +00:00
parent 976b093ecb
commit 6c865deedd
1 changed files with 90 additions and 0 deletions
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90
llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
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@ -2929,6 +2929,96 @@ define <8 x float> @unpckh_v8f32(<8 x float> %x, <8 x float> %y) {
ret <8 x float> %unpckh
}
; FIXME: AVX1 lowering is better than AVX2 (and AVX512?)
; Alternate form of the above - make sure we don't have conflicting transforms.
define <8 x i32> @blend_perm_v8i32(<8 x i32> %x, <8 x i32> %y) {
; AVX1-LABEL: blend_perm_v8i32:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: retq
;
; AVX2-LABEL: blend_perm_v8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = <2,6,3,7,u,u,u,u>
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: blend_perm_v8i32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = <2,14,3,15,u,u,u,u>
; AVX512VL-NEXT: vpermt2d %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%unpckh = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
%r = shufflevector <8 x i32> %unpckh, <8 x i32> undef, <8 x i32> <i32 2, i32 6, i32 3, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i32> %r
}
; FIXME: Same as above but with floats. AVX1 lowering is better than AVX2 (and AVX512?)
define <8 x float> @blend_perm_v8f32(<8 x float> %x, <8 x float> %y) {
; AVX1-LABEL: blend_perm_v8f32:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: retq
;
; AVX2-LABEL: blend_perm_v8f32:
; AVX2: # %bb.0:
; AVX2-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7]
; AVX2-NEXT: vmovaps {{.*#+}} ymm1 = <2,6,3,7,u,u,u,u>
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: retq
;
; AVX512VL-LABEL: blend_perm_v8f32:
; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vmovaps {{.*#+}} ymm2 = <2,14,3,15,u,u,u,u>
; AVX512VL-NEXT: vpermt2ps %ymm1, %ymm2, %ymm0
; AVX512VL-NEXT: retq
%unpckh = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 15>
%r = shufflevector <8 x float> %unpckh, <8 x float> undef, <8 x i32> <i32 2, i32 6, i32 3, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %r
}
; FIXME: AVX1 lowering is better than AVX2/AVX512.
; Another variation of the above - make sure we don't have conflicting transforms.
define <8 x i32> @unpckh_v8i32_unary(<8 x i32> %x) {
; AVX1-LABEL: unpckh_v8i32_unary:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: retq
;
; AVX2OR512VL-LABEL: unpckh_v8i32_unary:
; AVX2OR512VL: # %bb.0:
; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = <2,6,3,7,u,u,u,u>
; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq
%r = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 2, i32 6, i32 3, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i32> %r
}
; FIXME: Same as above but with floats. AVX1 lowering is better than AVX2/AVX512.
define <8 x float> @unpckh_v8f32_unary(<8 x float> %x) {
; AVX1-LABEL: unpckh_v8f32_unary:
; AVX1: # %bb.0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: retq
;
; AVX2OR512VL-LABEL: unpckh_v8f32_unary:
; AVX2OR512VL: # %bb.0:
; AVX2OR512VL-NEXT: vmovaps {{.*#+}} ymm1 = <2,6,3,7,u,u,u,u>
; AVX2OR512VL-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2OR512VL-NEXT: retq
%r = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 2, i32 6, i32 3, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x float> %r
}
; FIXME: Why are integer and FP (below) lowering different for AVX1?
define <8 x i32> @lowhalf_v8i32(<8 x i32> %x, <8 x i32> %y) {