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[X86] Add CMPSDrr/rm to the scheduler models. 

Somehow CMPSSrr/rm was there and the VEX version was there, but this was consistently missing.

llvm-svn: 320289
This commit is contained in:
Craig Topper 2017-12-10 09:14:37 +00:00
parent d435a1950f
commit 6c65910160
5 changed files with 10 additions and 0 deletions
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2
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -1291,6 +1291,7 @@ def: InstRW<[BWWriteResGroup27], (instregex "BSF(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CMPPDrri")>;
def: InstRW<[BWWriteResGroup27], (instregex "CMPPSrri")>;
def: InstRW<[BWWriteResGroup27], (instregex "CMPSDrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "CMPSSrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "COMISDrr")>;
def: InstRW<[BWWriteResGroup27], (instregex "COMISSrr")>;
@ -2769,6 +2770,7 @@ def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup91], (instregex "BSR(16|32|64)rm")>;
def: InstRW<[BWWriteResGroup91], (instregex "CMPPDrmi")>;
def: InstRW<[BWWriteResGroup91], (instregex "CMPPSrmi")>;
def: InstRW<[BWWriteResGroup91], (instregex "CMPSDrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "CMPSSrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "COMISDrm")>;
def: InstRW<[BWWriteResGroup91], (instregex "COMISSrm")>;

2
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -1586,6 +1586,7 @@ def: InstRW<[HWWriteResGroup12], (instregex "ADDSDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "ADDSSrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "BSF(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "BSR(16|32|64)rm")>;
def: InstRW<[HWWriteResGroup12], (instregex "CMPSDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "CMPSSrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "COMISDrm")>;
def: InstRW<[HWWriteResGroup12], (instregex "COMISSrm")>;
@ -2591,6 +2592,7 @@ def: InstRW<[HWWriteResGroup50], (instregex "BSF(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPPDrri")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPPSrri")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPSDrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "CMPSSrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "COMISDrr")>;
def: InstRW<[HWWriteResGroup50], (instregex "COMISSrr")>;

2
llvm/lib/Target/X86/X86SchedSandyBridge.td
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@ -975,6 +975,7 @@ def: InstRW<[SBWriteResGroup21], (instregex "BSF(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup21], (instregex "BSR(16|32|64)rr")>;
def: InstRW<[SBWriteResGroup21], (instregex "CMPPDrri")>;
def: InstRW<[SBWriteResGroup21], (instregex "CMPPSrri")>;
def: InstRW<[SBWriteResGroup21], (instregex "CMPSDrr")>;
def: InstRW<[SBWriteResGroup21], (instregex "CMPSSrr")>;
def: InstRW<[SBWriteResGroup21], (instregex "CRC32r(16|32|64)r8")>;
def: InstRW<[SBWriteResGroup21], (instregex "CRC32r(16|32|64)r64")>;
@ -2264,6 +2265,7 @@ def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPDrm")>;
def: InstRW<[SBWriteResGroup90], (instregex "ADDSUBPSrm")>;
def: InstRW<[SBWriteResGroup90], (instregex "CMPPDrmi")>;
def: InstRW<[SBWriteResGroup90], (instregex "CMPPSrmi")>;
def: InstRW<[SBWriteResGroup90], (instregex "CMPSDrm")>;
def: InstRW<[SBWriteResGroup90], (instregex "CMPSSrm")>;
def: InstRW<[SBWriteResGroup90], (instregex "CVTDQ2PSrm")>;
def: InstRW<[SBWriteResGroup90], (instregex "CVTPS2DQrm")>;

2
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -1721,6 +1721,7 @@ def SKLWriteResGroup49 : SchedWriteRes<[SKLPort015]> {
}
def: InstRW<[SKLWriteResGroup49], (instregex "CMPPDrri")>;
def: InstRW<[SKLWriteResGroup49], (instregex "CMPPSrri")>;
def: InstRW<[SKLWriteResGroup49], (instregex "CMPSDrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "CMPSSrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "CVTDQ2PSrr")>;
def: InstRW<[SKLWriteResGroup49], (instregex "CVTPS2DQrr")>;
@ -3116,6 +3117,7 @@ def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort015]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup123], (instregex "CMPSDrm")>;
def: InstRW<[SKLWriteResGroup123], (instregex "CMPSSrm")>;
def: InstRW<[SKLWriteResGroup123], (instregex "CVTPS2PDrm")>;
def: InstRW<[SKLWriteResGroup123], (instregex "MAX(C?)SDrm")>;

2
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -2405,6 +2405,7 @@ def: InstRW<[SKXWriteResGroup50], (instregex "ADDSUBPDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "ADDSUBPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CMPPDrri")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CMPPSrri")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CMPSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CMPSSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CVTDQ2PSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "CVTPS2DQrr")>;
@ -5062,6 +5063,7 @@ def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
}
def: InstRW<[SKXWriteResGroup137], (instregex "ADDSDrm")>;
def: InstRW<[SKXWriteResGroup137], (instregex "ADDSSrm")>;
def: InstRW<[SKXWriteResGroup137], (instregex "CMPSDrm")>;
def: InstRW<[SKXWriteResGroup137], (instregex "CMPSSrm")>;
def: InstRW<[SKXWriteResGroup137], (instregex "CVTPS2PDrm")>;
def: InstRW<[SKXWriteResGroup137], (instregex "MAX(C?)SDrm")>;