forked from OSchip/llvm-project
[PowerPC] Add compatibility check for PPC PLT stubs
Compatibility checks for PPC64PltCallStub and PPC64PCRelPLTStub are added in this patch to prevent the usage of incompatible thunk/stub. Reviewed By: sfertile, nemanjai, stefanp Differential Revision: https://reviews.llvm.org/D85459
This commit is contained in:
Victor Huang
parent
ffe1edfc53
commit
6c64f05b90
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@ -277,6 +277,8 @@ public:
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uint32_t size() override { return 20; }
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void writeTo(uint8_t *buf) override;
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void addSymbols(ThunkSection &isec) override;
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bool isCompatibleWith(const InputSection &isec,
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const Relocation &rel) const override;
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};
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// PPC64 R2 Save Stub
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@ -318,6 +320,8 @@ public:
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uint32_t size() override { return 16; }
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void writeTo(uint8_t *buf) override;
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void addSymbols(ThunkSection &isec) override;
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bool isCompatibleWith(const InputSection &isec,
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const Relocation &rel) const override;
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};
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// A bl instruction uses a signed 24 bit offset, with an implicit 4 byte
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@ -863,6 +867,11 @@ void PPC64PltCallStub::addSymbols(ThunkSection &isec) {
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s->file = destination.file;
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}
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bool PPC64PltCallStub::isCompatibleWith(const InputSection &isec,
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const Relocation &rel) const {
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return rel.type == R_PPC64_REL24 || rel.type == R_PPC64_REL14;
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}
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void PPC64R2SaveStub::writeTo(uint8_t *buf) {
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int64_t offset = destination.getVA() - (getThunkTargetSym()->getVA() + 4);
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// The branch offset needs to fit in 26 bits.
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@ -912,6 +921,11 @@ void PPC64PCRelPLTStub::addSymbols(ThunkSection &isec) {
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isec);
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}
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bool PPC64PCRelPLTStub::isCompatibleWith(const InputSection &isec,
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const Relocation &rel) const {
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return rel.type == R_PPC64_REL24_NOTOC;
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}
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void PPC64LongBranchThunk::writeTo(uint8_t *buf) {
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int64_t offset = in.ppc64LongBranchTarget->getEntryVA(&destination, addend) -
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getPPC64TocBase();
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@ -0,0 +1,126 @@
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# REQUIRES: ppc
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# RUN: echo 'SECTIONS { \
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# RUN: .text_start 0x10010300 : { *(.text_start) } \
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# RUN: }' > %t.script
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T1=1 -o %t1.o
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T2=1 -o %t2.o
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# RUN: llvm-mc -filetype=obj -triple=powerpc64le %s --defsym T3=1 -o %t3.o
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# RUN: ld.lld --shared %t1.o -o %t1.so
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# RUN: ld.lld -T %t.script %t1.so %t2.o -o %t2
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# RUN: ld.lld -T %t.script %t1.so %t3.o -o %t3
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# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t2 | FileCheck %s --check-prefix=T2
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# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t3 | FileCheck %s --check-prefix=T3
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# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T1=1 -o %t1.o
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# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T2=1 -o %t2.o
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# RUN: llvm-mc -filetype=obj -triple=powerpc64 %s --defsym T3=1 -o %t3.o
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# RUN: ld.lld --shared %t1.o -o %t1.so
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# RUN: ld.lld -T %t.script %t1.so %t2.o -o %t2
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# RUN: ld.lld -T %t.script %t1.so %t3.o -o %t3
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# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t2 | FileCheck %s --check-prefix=T2
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# RUN: llvm-objdump -d --no-show-raw-insn --mcpu=pwr10 %t3 | FileCheck %s --check-prefix=T3
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.ifdef T1
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.globl callee
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callee:
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blr
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.endif
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# T2-LABEL: <p9codegen>:
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# T2-NEXT: 10010300: addis 2, 12, 1
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# T2-NEXT: 10010304: addi 2, 2, -32392
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# T2-NEXT: 10010308: addis 4, 2, -1
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# T2-NEXT: 1001030c: lwa 3, 32436(4)
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# T2-NEXT: 10010310: bl 0x10010330
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# T2-NEXT: 10010314: ld 2, 24(1)
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# T2-NEXT: 10010318: blr
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# T2-LABEL: <p10codegen>:
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# T2-NEXT: 1001031c: plwa 3, 16(0), 1
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# T2-NEXT: 10010324: bl 0x10010344
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# T2-NEXT: 10010328: blr
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# T2-LABEL: <__plt_callee>:
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# T2-NEXT: 10010330: std 2, 24(1)
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# T2-NEXT: 10010334: addis 12, 2, 0
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# T2-NEXT: 10010338: ld 12, -32744(12)
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# T2-NEXT: 1001033c: mtctr 12
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# T2-NEXT: 10010340: bctr
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# T2-LABEL: <__plt_pcrel_callee>:
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# T2-NEXT: 10010344: pld 12, 332(0), 1
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# T2-NEXT: 1001034c: mtctr 12
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# T2-NEXT: 10010350: bctr
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.ifdef T2
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.section .text_start, "ax", %progbits
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p9codegen:
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.Lfunc_gep0:
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addis 2, 12, .TOC.-.Lfunc_gep0@ha
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addi 2, 2, .TOC.-.Lfunc_gep0@l
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.Lfunc_lep0:
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.localentry p9codegen, .Lfunc_lep0-.Lfunc_gep0
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addis 4, 2, Global@toc@ha
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lwa 3, Global@toc@l(4)
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bl callee
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nop
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blr
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p10codegen:
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.localentry main, 1
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plwa 3, Global@PCREL(0), 1
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bl callee@notoc
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blr
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.globl Global
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Global:
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.long 10
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.size Global, 4
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.endif
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# T3-LABEL: <p10codegen>:
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# T3-NEXT: 10010300: plwa 3, 44(0), 1
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# T3-NEXT: 10010308: bl 0x10010330
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# T3-NEXT: 1001030c: blr
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# T3-LABEL: <p9codegen>:
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# T3-NEXT: 10010310: addis 2, 12, 1
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# T3-NEXT: 10010314: addi 2, 2, -32408
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# T3-NEXT: 10010318: addis 4, 2, -1
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# T3-NEXT: 1001031c: lwa 3, 32436(4)
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# T3-NEXT: 10010320: bl 0x10010340
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# T3-NEXT: 10010324: ld 2, 24(1)
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# T3-NEXT: 10010328: blr
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# T3-LABEL: <__plt_pcrel_callee>:
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# T3-NEXT: 10010330: pld 12, 352(0), 1
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# T3-NEXT: 10010338: mtctr 12
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# T3-NEXT: 1001033c: bctr
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# T3-LABEL: <__plt_callee>:
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# T3-NEXT: 10010340: std 2, 24(1)
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# T3-NEXT: 10010344: addis 12, 2, 0
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# T3-NEXT: 10010348: ld 12, -32744(12)
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# T3-NEXT: 1001034c: mtctr 12
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# T3-NEXT: 10010350: bctr
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.ifdef T3
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.section .text_start, "ax", %progbits
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p10codegen:
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.localentry main, 1
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plwa 3, Global@PCREL(0), 1
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bl callee@notoc
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blr
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p9codegen:
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.Lfunc_gep0:
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addis 2, 12, .TOC.-.Lfunc_gep0@ha
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addi 2, 2, .TOC.-.Lfunc_gep0@l
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.Lfunc_lep0:
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.localentry p9codegen, .Lfunc_lep0-.Lfunc_gep0
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addis 4, 2, Global@toc@ha
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lwa 3, Global@toc@l(4)
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bl callee
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nop
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blr
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.globl Global
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Global:
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.long 10
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.size Global, 4
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.endif
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