forked from OSchip/llvm-project
[VE] Change to expand BRCOND
VE doesn't have BRCOND instruction, so need to expand it. Also add a regression test. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89173
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@ -679,6 +679,11 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
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/// } Stack
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/// Branch {
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// VE doesn't have BRCOND
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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/// } Branch
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/// Int Ops {
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for (MVT IntVT : {MVT::i32, MVT::i64}) {
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// VE has no REM or DIVREM operations.
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@ -0,0 +1,43 @@
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; RUN: llc < %s -mtriple=ve | FileCheck %s
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; Function Attrs: nounwind
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define void @test_then(i1 zeroext %0) {
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; CHECK-LABEL: test_then:
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; CHECK: .LBB{{[0-9]+}}_4:
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; CHECK-NEXT: breq.w 0, %s0, .LBB{{[0-9]+}}_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s11, 0, %s9
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br i1 %0, label %2, label %3
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2: ; preds = %1
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tail call void asm sideeffect "nop", ""()
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br label %3
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3: ; preds = %2, %1
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ret void
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}
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; Function Attrs: nounwind
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define void @test_else(i1 zeroext %0) {
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; CHECK-LABEL: test_else:
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; CHECK: .LBB{{[0-9]+}}_4:
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; CHECK-NEXT: brne.w 0, %s0, .LBB{{[0-9]+}}_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: #APP
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; CHECK-NEXT: nop
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s11, 0, %s9
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br i1 %0, label %3, label %2
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2: ; preds = %1
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tail call void asm sideeffect "nop", ""()
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br label %3
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3: ; preds = %2, %1
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ret void
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}
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