maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

InstCombine: Flip the order of two urem transforms 

There are two transforms in visitUrem that conflict with each other.

*) One, if a divisor is a power of two, subtracts one from the divisor
   and turns it into a bitwise-and.
*) The other unwraps both operands if they are surrounded by zext
   instructions.

Flipping the order allows the subtraction to go beneath the sign
extension.

llvm-svn: 181668
This commit is contained in:
David Majnemer 2013-05-12 00:07:05 +00:00
parent f2305e4467
commit 6c30f49af3
2 changed files with 20 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
View File

@ -1027,6 +1027,12 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
if (Instruction *common = commonIRemTransforms(I)) if (Instruction *common = commonIRemTransforms(I))
return common; return common;
// (zext A) urem (zext B) --> zext (A urem B)
if (ZExtInst *ZOp0 = dyn_cast<ZExtInst>(Op0))
if (Value *ZOp1 = dyn_castZExtVal(Op1, ZOp0->getSrcTy()))
return new ZExtInst(Builder->CreateURem(ZOp0->getOperand(0), ZOp1),
I.getType());
// X urem Y -> X and Y-1, where Y is a power of 2, // X urem Y -> X and Y-1, where Y is a power of 2,
if (isKnownToBeAPowerOfTwo(Op1, /*OrZero*/true)) { if (isKnownToBeAPowerOfTwo(Op1, /*OrZero*/true)) {
Constant *N1 = Constant::getAllOnesValue(I.getType()); Constant *N1 = Constant::getAllOnesValue(I.getType());
@ -1034,12 +1040,6 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
return BinaryOperator::CreateAnd(Op0, Add); return BinaryOperator::CreateAnd(Op0, Add);
} }
// (zext A) urem (zext B) --> zext (A urem B)
if (ZExtInst *ZOp0 = dyn_cast<ZExtInst>(Op0))
if (Value *ZOp1 = dyn_castZExtVal(Op1, ZOp0->getSrcTy()))
return new ZExtInst(Builder->CreateURem(ZOp0->getOperand(0), ZOp1),
I.getType());
return 0; return 0;
} }

14
llvm/test/Transforms/InstCombine/rem.ll
View File

@ -135,3 +135,17 @@ define i64 @test14(i64 %x, i32 %y) {
%urem = urem i64 %x, %zext %urem = urem i64 %x, %zext
ret i64 %urem ret i64 %urem
} }
define i64 @test15(i32 %x, i32 %y) {
; CHECK: @test15
; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, %y
; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], -1
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ADD]], %x
; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[AND]] to i64
; CHECK-NEXT: ret i64 [[ZEXT]]
%shl = shl i32 1, %y
%zext0 = zext i32 %shl to i64
%zext1 = zext i32 %x to i64
%urem = urem i64 %zext1, %zext0
ret i64 %urem
}