forked from OSchip/llvm-project
[WebAssembly] Expand SIMD shifts while V8's implementation disagrees
Summary: V8 currently implements SIMD shifts as taking an immediate operation, which disagrees with the spec proposal and the toolchain implementation. As a stopgap measure to get things working, unroll all vector shifts. Since this is a temporary measure, there are no tests. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, dmgreen, llvm-commits Differential Revision: https://reviews.llvm.org/D56520 llvm-svn: 351151
This commit is contained in:
Thomas Lively
parent
33eb4d947d
commit
6bf2b40051
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@ -1155,6 +1155,31 @@ WebAssemblyTargetLowering::LowerAccessVectorElement(SDValue Op,
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return SDValue();
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}
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static SDValue UnrollVectorShift(SDValue Op, SelectionDAG &DAG) {
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EVT LaneT = Op.getSimpleValueType().getVectorElementType();
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// 32-bit and 64-bit unrolled shifts will have proper semantics
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if (LaneT.bitsGE(MVT::i32))
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return DAG.UnrollVectorOp(Op.getNode());
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// Otherwise mask the shift value to get proper semantics from 32-bit shift
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SDLoc DL(Op);
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SDValue ShiftVal = Op.getOperand(1);
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uint64_t MaskVal = LaneT.getSizeInBits() - 1;
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SDValue MaskedShiftVal = DAG.getNode(
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ISD::AND, // mask opcode
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DL, ShiftVal.getValueType(), // masked value type
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ShiftVal, // original shift value operand
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DAG.getConstant(MaskVal, DL, ShiftVal.getValueType()) // mask operand
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);
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return DAG.UnrollVectorOp(
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DAG.getNode(Op.getOpcode(), // original shift opcode
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DL, Op.getValueType(), // original return type
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Op.getOperand(0), // original vector operand,
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MaskedShiftVal // new masked shift value operand
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)
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.getNode());
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}
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SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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@ -1162,12 +1187,17 @@ SDValue WebAssemblyTargetLowering::LowerShift(SDValue Op,
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// Only manually lower vector shifts
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assert(Op.getSimpleValueType().isVector());
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// Expand all vector shifts until V8 fixes its implementation
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// TODO: remove this once V8 is fixed
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if (!Subtarget->hasUnimplementedSIMD128())
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return UnrollVectorShift(Op, DAG);
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// Unroll non-splat vector shifts
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BuildVectorSDNode *ShiftVec;
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SDValue SplatVal;
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if (!(ShiftVec = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode())) ||
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!(SplatVal = ShiftVec->getSplatValue()))
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return DAG.UnrollVectorOp(Op.getNode());
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return UnrollVectorShift(Op, DAG);
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// All splats except i64x2 const splats are handled by patterns
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ConstantSDNode *SplatConst = dyn_cast<ConstantSDNode>(SplatVal);
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@ -90,7 +90,11 @@ define <16 x i8> @shl_const_v16i8(<16 x i8> %v) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128-NEXT: .functype shl_vec_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 14 lanes
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@ -122,7 +126,11 @@ define <16 x i8> @shr_s_v16i8(<16 x i8> %v, i8 %x) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128-NEXT: .functype shr_s_vec_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 14 lanes
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@ -154,7 +162,11 @@ define <16 x i8> @shr_u_v16i8(<16 x i8> %v, i8 %x) {
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; NO-SIMD128-NOT: i8x16
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; SIMD128-NEXT: .functype shr_u_vec_v16i8 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 7{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i8x16.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i8x16.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 14 lanes
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@ -304,7 +316,11 @@ define <8 x i16> @shl_const_v8i16(<8 x i16> %v) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype shl_vec_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shl $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 6 lanes
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@ -335,7 +351,11 @@ define <8 x i16> @shr_s_v8i16(<8 x i16> %v, i16 %x) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype shr_s_vec_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.extract_lane_s $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shr_s $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 6 lanes
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@ -366,7 +386,11 @@ define <8 x i16> @shr_u_v8i16(<8 x i16> %v, i16 %x) {
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; NO-SIMD128-NOT: i16x8
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; SIMD128-NEXT: .functype shr_u_vec_v8i16 (v128, v128) -> (v128){{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L0:[0-9]+]]=, $0, 0{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $1, 0{{$}}
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; SIMD128-NEXT: i32.const $push[[M0:[0-9]+]]=, 15{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[M1:[0-9]+]]=, $pop[[M0]]{{$}}
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; SIMD128-NEXT: v128.and $push[[M2:[0-9]+]]=, $1, $pop[[M1]]{{$}}
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; SIMD128-NEXT: local.tee $push[[M:[0-9]+]]=, $1=, $pop[[M2]]{{$}}
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; SIMD128-NEXT: i16x8.extract_lane_u $push[[L1:[0-9]+]]=, $pop[[M]], 0{{$}}
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; SIMD128-NEXT: i32.shr_u $push[[L2:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
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; SIMD128-NEXT: i16x8.splat $push[[L3:[0-9]+]]=, $pop[[L2]]{{$}}
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; Skip 6 lanes
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