forked from OSchip/llvm-project
parent
8704057ce9
commit
6bc772eec7
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@ -165,6 +165,10 @@ def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
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def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
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def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
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// FIXME: move this to a more appropriate place after all AVX is done.
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def memopv8f32 : PatFrag<(ops node:$ptr), (v8f32 (memop node:$ptr))>;
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def memopv4f64 : PatFrag<(ops node:$ptr), (v4f64 (memop node:$ptr))>;
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// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
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// 16-byte boundary.
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// FIXME: 8 byte alignment for mmx reads is not required
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@ -1539,6 +1543,19 @@ let AddedComplexity = 10 in {
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defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
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VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
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VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
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VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, VEX_4V;
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defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
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VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, OpSize, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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@ -12354,3 +12354,35 @@
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// CHECK: encoding: [0xc5,0xfd,0x11,0x08]
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vmovupd %ymm1, (%eax)
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// CHECK: vunpckhps %ymm1, %ymm2, %ymm4
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// CHECK: encoding: [0xc5,0xec,0x15,0xe1]
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vunpckhps %ymm1, %ymm2, %ymm4
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// CHECK: vunpckhpd %ymm1, %ymm2, %ymm4
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// CHECK: encoding: [0xc5,0xed,0x15,0xe1]
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vunpckhpd %ymm1, %ymm2, %ymm4
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// CHECK: vunpcklps %ymm1, %ymm2, %ymm4
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// CHECK: encoding: [0xc5,0xec,0x14,0xe1]
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vunpcklps %ymm1, %ymm2, %ymm4
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// CHECK: vunpcklpd %ymm1, %ymm2, %ymm4
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// CHECK: encoding: [0xc5,0xed,0x14,0xe1]
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vunpcklpd %ymm1, %ymm2, %ymm4
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// CHECK: vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: encoding: [0xc5,0xec,0x15,0x6c,0xcb,0xfc]
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vunpckhps -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: encoding: [0xc5,0xed,0x15,0x6c,0xcb,0xfc]
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vunpckhpd -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: encoding: [0xc5,0xec,0x14,0x6c,0xcb,0xfc]
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vunpcklps -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5
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// CHECK: encoding: [0xc5,0xed,0x14,0x6c,0xcb,0xfc]
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vunpcklpd -4(%ebx,%ecx,8), %ymm2, %ymm5
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@ -2428,3 +2428,35 @@ pshufb CPI1_0(%rip), %xmm1
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// CHECK: encoding: [0xc5,0x7d,0x11,0x18]
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vmovupd %ymm11, (%rax)
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// CHECK: vunpckhps %ymm11, %ymm12, %ymm4
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// CHECK: encoding: [0xc4,0xc1,0x1c,0x15,0xe3]
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vunpckhps %ymm11, %ymm12, %ymm4
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// CHECK: vunpckhpd %ymm11, %ymm12, %ymm4
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// CHECK: encoding: [0xc4,0xc1,0x1d,0x15,0xe3]
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vunpckhpd %ymm11, %ymm12, %ymm4
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// CHECK: vunpcklps %ymm11, %ymm12, %ymm4
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// CHECK: encoding: [0xc4,0xc1,0x1c,0x14,0xe3]
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vunpcklps %ymm11, %ymm12, %ymm4
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// CHECK: vunpcklpd %ymm11, %ymm12, %ymm4
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// CHECK: encoding: [0xc4,0xc1,0x1d,0x14,0xe3]
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vunpcklpd %ymm11, %ymm12, %ymm4
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// CHECK: vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: encoding: [0xc5,0x1c,0x15,0x54,0xcb,0xfc]
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vunpckhps -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: encoding: [0xc5,0x1d,0x15,0x54,0xcb,0xfc]
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vunpckhpd -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: encoding: [0xc5,0x1c,0x14,0x54,0xcb,0xfc]
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vunpcklps -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10
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// CHECK: encoding: [0xc5,0x1d,0x14,0x54,0xcb,0xfc]
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vunpcklpd -4(%rbx,%rcx,8), %ymm12, %ymm10
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