forked from OSchip/llvm-project
[C++11] Add 'override' keyword to virtual methods that override their base class.
llvm-svn: 203433
This commit is contained in:
parent
245b7fd3f2
commit
6bc27bf359
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@ -49,9 +49,9 @@ namespace {
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static char ID;
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A15SDOptimizer() : MachineFunctionPass(ID) {}
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virtual bool runOnMachineFunction(MachineFunction &Fn);
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bool runOnMachineFunction(MachineFunction &Fn) override;
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virtual const char *getPassName() const {
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const char *getPassName() const override {
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return "ARM A15 S->D optimizer";
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}
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@ -42,37 +42,37 @@ public:
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// if there is not such an opcode.
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virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const;
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MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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LiveVariables *LV) const override;
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virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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const ARMSubtarget &getSubtarget() const { return Subtarget; }
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ScheduleHazardRecognizer *
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CreateTargetHazardRecognizer(const TargetMachine *TM,
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const ScheduleDAG *DAG) const;
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const ScheduleDAG *DAG) const override;
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ScheduleHazardRecognizer *
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CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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const ScheduleDAG *DAG) const;
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const ScheduleDAG *DAG) const override;
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// Branch analysis.
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const override;
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virtual
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bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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// Predication support.
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bool isPredicated(const MachineInstr *MI) const;
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bool isPredicated(const MachineInstr *MI) const override;
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ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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int PIdx = MI->findFirstPredOperandIdx();
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@ -80,76 +80,73 @@ public:
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: ARMCC::AL;
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}
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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const SmallVectorImpl<MachineOperand> &Pred) const override;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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const SmallVectorImpl<MachineOperand> &Pred2) const override;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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virtual bool isPredicable(MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const override;
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/// GetInstSize - Returns the size of the specified MachineInstr.
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///
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virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const override;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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virtual void reMaterialize(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig,
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const TargetRegisterInfo &TRI) const override;
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MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
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MachineInstr *duplicate(MachineInstr *Orig,
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MachineFunction &MF) const override;
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MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
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MachineInstr *commuteInstruction(MachineInstr*,
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bool=false) const override;
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const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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unsigned SubIdx, unsigned State,
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const TargetRegisterInfo *TRI) const;
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virtual bool produceSameValue(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const;
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bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const override;
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/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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/// determine if two loads are loading from the same base address. It should
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/// only return true if the base pointers are the same and the only
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/// differences between the two addresses is the offset. It also returns the
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/// offsets by reference.
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virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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int64_t &Offset1, int64_t &Offset2)const;
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bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
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int64_t &Offset2) const override;
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/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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@ -159,83 +156,79 @@ public:
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/// from the common base address. It returns true if it decides it's desirable
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/// to schedule the two loads together. "NumLoads" is the number of loads that
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/// have already been scheduled after Load1.
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virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const;
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bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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int64_t Offset1, int64_t Offset2,
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unsigned NumLoads) const override;
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virtual bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const;
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bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles, unsigned ExtraPredCycles,
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const BranchProbability &Probability) const override;
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virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumT, unsigned ExtraT,
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MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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const BranchProbability &Probability) const;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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unsigned ExtraT, MachineBasicBlock &FMBB,
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unsigned NumF, unsigned ExtraF,
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const BranchProbability &Probability) const override;
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virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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unsigned NumCycles,
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const BranchProbability
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&Probability) const {
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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const BranchProbability &Probability) const override {
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return NumCycles == 1;
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}
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virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const;
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bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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MachineBasicBlock &FMBB) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2 if having two register operands, and the value it
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/// compares against in CmpValue. Return true if the comparison instruction
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/// can be analyzed.
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virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const;
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bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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unsigned &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction to set the zero flag so
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/// that we can remove a "comparison with zero"; Remove a redundant CMP
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/// instruction if the flags can be updated in the same way by an earlier
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/// instruction such as SUB.
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virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const;
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bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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unsigned SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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virtual bool analyzeSelect(const MachineInstr *MI,
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SmallVectorImpl<MachineOperand> &Cond,
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unsigned &TrueOp, unsigned &FalseOp,
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bool &Optimizable) const;
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bool analyzeSelect(const MachineInstr *MI,
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SmallVectorImpl<MachineOperand> &Cond,
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unsigned &TrueOp, unsigned &FalseOp,
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bool &Optimizable) const override;
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virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
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MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
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/// FoldImmediate - 'Reg' is known to be defined by a move immediate
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/// instruction, try to fold the immediate into the use instruction.
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virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const;
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bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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unsigned Reg, MachineRegisterInfo *MRI) const override;
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virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const;
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unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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const MachineInstr *MI) const override;
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virtual
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int getOperandLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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virtual
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const MachineInstr *UseMI,
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unsigned UseIdx) const override;
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int getOperandLatency(const InstrItineraryData *ItinData,
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SDNode *DefNode, unsigned DefIdx,
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SDNode *UseNode, unsigned UseIdx) const;
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SDNode *UseNode, unsigned UseIdx) const override;
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/// VFP/NEON execution domains.
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std::pair<uint16_t, uint16_t>
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getExecutionDomain(const MachineInstr *MI) const;
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void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
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getExecutionDomain(const MachineInstr *MI) const override;
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void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
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unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
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const TargetRegisterInfo*) const;
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const TargetRegisterInfo*) const override;
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void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
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const TargetRegisterInfo *TRI) const;
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const TargetRegisterInfo *TRI) const override;
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/// Get the number of addresses by LDM or VLDM or zero for unknown.
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unsigned getNumLDMAddresses(const MachineInstr *MI) const;
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const MCInstrDesc &UseMCID,
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unsigned UseIdx, unsigned UseAlign) const;
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unsigned getPredicationCost(const MachineInstr *MI) const;
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unsigned getPredicationCost(const MachineInstr *MI) const override;
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unsigned getInstrLatency(const InstrItineraryData *ItinData,
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const MachineInstr *MI,
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unsigned *PredCost = 0) const;
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unsigned *PredCost = 0) const override;
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int getInstrLatency(const InstrItineraryData *ItinData,
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SDNode *Node) const;
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SDNode *Node) const override;
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bool hasHighOperandLatency(const InstrItineraryData *ItinData,
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const MachineRegisterInfo *MRI,
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const MachineInstr *DefMI, unsigned DefIdx,
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const MachineInstr *UseMI, unsigned UseIdx) const;
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const MachineInstr *UseMI,
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unsigned UseIdx) const override;
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bool hasLowDefLatency(const InstrItineraryData *ItinData,
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const MachineInstr *DefMI, unsigned DefIdx) const;
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const MachineInstr *DefMI,
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unsigned DefIdx) const override;
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/// verifyInstruction - Perform target specific instruction verification.
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bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
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bool verifyInstruction(const MachineInstr *MI,
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StringRef &ErrInfo) const override;
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private:
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/// Modeling special VFP / NEON fp MLA / MLS hazards.
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@ -100,8 +100,9 @@ protected:
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public:
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/// Code Generation virtual methods...
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const;
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const uint16_t *
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getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
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const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
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const uint32_t *getNoPreservedMask() const;
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/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
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/// Should return NULL in the case that the calling convention does not have
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/// this property
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const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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const TargetRegisterClass*
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getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
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const TargetRegisterClass*
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getCrossCopyRegClass(const TargetRegisterClass *RC) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const TargetRegisterClass*
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
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const TargetRegisterClass *
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getPointerRegClass(const MachineFunction &MF,
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unsigned Kind = 0) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
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const TargetRegisterClass *
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getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const;
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MachineFunction &MF) const override;
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void getRegAllocationHints(unsigned VirtReg,
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ArrayRef<MCPhysReg> Order,
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SmallVectorImpl<MCPhysReg> &Hints,
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const MachineFunction &MF,
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const VirtRegMap *VRM) const;
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const VirtRegMap *VRM) const override;
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void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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MachineFunction &MF) const;
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MachineFunction &MF) const override;
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virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
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bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
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bool hasBasePointer(const MachineFunction &MF) const;
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bool canRealignStack(const MachineFunction &MF) const;
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bool needsStackRealignment(const MachineFunction &MF) const;
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
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bool needsStackRealignment(const MachineFunction &MF) const override;
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const;
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int64_t Offset) const override;
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void resolveFrameIndex(MachineBasicBlock::iterator I,
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unsigned BaseReg, int64_t Offset) const;
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bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
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unsigned BaseReg, int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI,
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int64_t Offset) const override;
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bool cannotEliminateFrame(const MachineFunction &MF) const;
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// Debug information queries.
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unsigned getFrameRegister(const MachineFunction &MF) const;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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unsigned getBaseRegister() const { return BasePtr; }
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bool isLowRegister(unsigned Reg) const;
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/// specified immediate.
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virtual void emitLoadConstPool(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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unsigned DestReg, unsigned SubIdx,
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int Val,
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ARMCC::CondCodes Pred = ARMCC::AL,
|
||||
DebugLoc dl, unsigned DestReg, unsigned SubIdx,
|
||||
int Val, ARMCC::CondCodes Pred = ARMCC::AL,
|
||||
unsigned PredReg = 0,
|
||||
unsigned MIFlags = MachineInstr::NoFlags)const;
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
virtual bool mayOverrideLocalAssignment() const;
|
||||
bool mayOverrideLocalAssignment() const override;
|
||||
|
||||
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
|
||||
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
|
||||
|
||||
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
|
||||
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
|
||||
|
||||
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
|
||||
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
|
||||
|
||||
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
|
||||
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
|
||||
|
||||
virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = NULL) const;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = NULL) const override;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
@ -57,7 +57,7 @@ namespace {
|
|||
bool IsPIC;
|
||||
bool IsThumb;
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.addRequired<MachineModuleInfo>();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
@ -76,9 +76,9 @@ namespace {
|
|||
/// machine instructions.
|
||||
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
|
||||
|
||||
bool runOnMachineFunction(MachineFunction &MF);
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM Machine Code Emitter";
|
||||
}
|
||||
|
||||
|
|
|
@ -266,9 +266,9 @@ namespace {
|
|||
static char ID;
|
||||
ARMConstantIslands() : MachineFunctionPass(ID) {}
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &MF);
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM constant island placement and branch shortening pass";
|
||||
}
|
||||
|
||||
|
|
|
@ -103,12 +103,12 @@ public:
|
|||
bool isLSDA() const { return Kind == ARMCP::CPLSDA; }
|
||||
bool isMachineBasicBlock() const{ return Kind == ARMCP::CPMachineBasicBlock; }
|
||||
|
||||
virtual unsigned getRelocationInfo() const { return 2; }
|
||||
unsigned getRelocationInfo() const override { return 2; }
|
||||
|
||||
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment);
|
||||
int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment) override;
|
||||
|
||||
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
|
||||
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
|
||||
|
||||
/// hasSameValue - Return true if this ARM constpool value can share the same
|
||||
/// constantpool entry as another ARM constpool value.
|
||||
|
@ -120,7 +120,7 @@ public:
|
|||
this->Modifier == A->Modifier;
|
||||
}
|
||||
|
||||
virtual void print(raw_ostream &O) const;
|
||||
void print(raw_ostream &O) const override;
|
||||
void print(raw_ostream *O) const { if (O) print(*O); }
|
||||
void dump() const;
|
||||
};
|
||||
|
@ -164,16 +164,16 @@ public:
|
|||
const GlobalValue *getGV() const;
|
||||
const BlockAddress *getBlockAddress() const;
|
||||
|
||||
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment);
|
||||
int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment) override;
|
||||
|
||||
/// hasSameValue - Return true if this ARM constpool value can share the same
|
||||
/// constantpool entry as another ARM constpool value.
|
||||
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
|
||||
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
|
||||
|
||||
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
|
||||
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
|
||||
|
||||
virtual void print(raw_ostream &O) const;
|
||||
void print(raw_ostream &O) const override;
|
||||
static bool classof(const ARMConstantPoolValue *APV) {
|
||||
return APV->isGlobalValue() || APV->isBlockAddress() || APV->isLSDA();
|
||||
}
|
||||
|
@ -198,16 +198,16 @@ public:
|
|||
|
||||
const char *getSymbol() const { return S.c_str(); }
|
||||
|
||||
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment);
|
||||
int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment) override;
|
||||
|
||||
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
|
||||
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
|
||||
|
||||
/// hasSameValue - Return true if this ARM constpool value can share the same
|
||||
/// constantpool entry as another ARM constpool value.
|
||||
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
|
||||
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
|
||||
|
||||
virtual void print(raw_ostream &O) const;
|
||||
void print(raw_ostream &O) const override;
|
||||
|
||||
static bool classof(const ARMConstantPoolValue *ACPV) {
|
||||
return ACPV->isExtSymbol();
|
||||
|
@ -234,16 +234,16 @@ public:
|
|||
|
||||
const MachineBasicBlock *getMBB() const { return MBB; }
|
||||
|
||||
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment);
|
||||
int getExistingMachineCPValue(MachineConstantPool *CP,
|
||||
unsigned Alignment) override;
|
||||
|
||||
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
|
||||
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
|
||||
|
||||
/// hasSameValue - Return true if this ARM constpool value can share the same
|
||||
/// constantpool entry as another ARM constpool value.
|
||||
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
|
||||
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
|
||||
|
||||
virtual void print(raw_ostream &O) const;
|
||||
void print(raw_ostream &O) const override;
|
||||
|
||||
static bool classof(const ARMConstantPoolValue *ACPV) {
|
||||
return ACPV->isMachineBasicBlock();
|
||||
|
|
|
@ -46,9 +46,9 @@ namespace {
|
|||
const ARMSubtarget *STI;
|
||||
ARMFunctionInfo *AFI;
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM pseudo instruction expansion pass";
|
||||
}
|
||||
|
||||
|
|
|
@ -144,12 +144,12 @@ class ARMFastISel : public FastISel {
|
|||
|
||||
// Backend specific FastISel code.
|
||||
private:
|
||||
virtual bool TargetSelectInstruction(const Instruction *I);
|
||||
virtual unsigned TargetMaterializeConstant(const Constant *C);
|
||||
virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
|
||||
virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
|
||||
const LoadInst *LI);
|
||||
virtual bool FastLowerArguments();
|
||||
bool TargetSelectInstruction(const Instruction *I) override;
|
||||
unsigned TargetMaterializeConstant(const Constant *C) override;
|
||||
unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
|
||||
bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
|
||||
const LoadInst *LI) override;
|
||||
bool FastLowerArguments() override;
|
||||
private:
|
||||
#include "ARMGenFastISel.inc"
|
||||
|
||||
|
|
|
@ -33,31 +33,30 @@ public:
|
|||
|
||||
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
|
||||
/// the function.
|
||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
void emitPrologue(MachineFunction &MF) const override;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
|
||||
|
||||
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const;
|
||||
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
|
||||
bool hasFP(const MachineFunction &MF) const override;
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const override;
|
||||
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
|
||||
int getFrameIndexReference(const MachineFunction &MF, int FI,
|
||||
unsigned &FrameReg) const;
|
||||
int ResolveFrameIndexReference(const MachineFunction &MF,
|
||||
int FI,
|
||||
unsigned &FrameReg) const override;
|
||||
int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
|
||||
unsigned &FrameReg, int SPAdj) const;
|
||||
int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
|
||||
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
|
||||
|
||||
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
|
||||
RegScavenger *RS) const;
|
||||
RegScavenger *RS) const override;
|
||||
|
||||
private:
|
||||
void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||
|
@ -71,10 +70,10 @@ public:
|
|||
bool(*Func)(unsigned, bool),
|
||||
unsigned NumAlignedDPRCS2Regs) const;
|
||||
|
||||
virtual void eliminateCallFramePseudoInstr(
|
||||
MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const;
|
||||
void
|
||||
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const override;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
|
|
@ -37,11 +37,11 @@ public:
|
|||
: ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
|
||||
LastMI(0) {}
|
||||
|
||||
virtual HazardType getHazardType(SUnit *SU, int Stalls);
|
||||
virtual void Reset();
|
||||
virtual void EmitInstruction(SUnit *SU);
|
||||
virtual void AdvanceCycle();
|
||||
virtual void RecedeCycle();
|
||||
HazardType getHazardType(SUnit *SU, int Stalls) override;
|
||||
void Reset() override;
|
||||
void EmitInstruction(SUnit *SU) override;
|
||||
void AdvanceCycle() override;
|
||||
void RecedeCycle() override;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
@ -73,11 +73,11 @@ public:
|
|||
Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
|
||||
}
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM Instruction Selection";
|
||||
}
|
||||
|
||||
virtual void PreprocessISelDAG();
|
||||
void PreprocessISelDAG() override;
|
||||
|
||||
/// getI32Imm - Return a target constant of type i32 with the specified
|
||||
/// value.
|
||||
|
@ -85,7 +85,7 @@ public:
|
|||
return CurDAG->getTargetConstant(Imm, MVT::i32);
|
||||
}
|
||||
|
||||
SDNode *Select(SDNode *N);
|
||||
SDNode *Select(SDNode *N) override;
|
||||
|
||||
|
||||
bool hasNoVMLxHazardUse(SDNode *N) const;
|
||||
|
@ -257,9 +257,8 @@ private:
|
|||
|
||||
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
|
||||
/// inline asm expressions.
|
||||
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
|
||||
char ConstraintCode,
|
||||
std::vector<SDValue> &OutOps);
|
||||
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
|
||||
std::vector<SDValue> &OutOps) override;
|
||||
|
||||
// Form pairs of consecutive R, S, D, or Q registers.
|
||||
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
|
||||
|
|
|
@ -234,117 +234,114 @@ namespace llvm {
|
|||
public:
|
||||
explicit ARMTargetLowering(TargetMachine &TM);
|
||||
|
||||
virtual unsigned getJumpTableEncoding() const;
|
||||
unsigned getJumpTableEncoding() const override;
|
||||
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
|
||||
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
|
||||
|
||||
/// ReplaceNodeResults - Replace the results of node with an illegal result
|
||||
/// type with new values built out of custom code.
|
||||
///
|
||||
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
||||
SelectionDAG &DAG) const;
|
||||
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
const char *getTargetNodeName(unsigned Opcode) const override;
|
||||
|
||||
virtual bool isSelectSupported(SelectSupportKind Kind) const {
|
||||
bool isSelectSupported(SelectSupportKind Kind) const override {
|
||||
// ARM does not support scalar condition selects on vectors.
|
||||
return (Kind != ScalarCondVectorVal);
|
||||
}
|
||||
|
||||
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
|
||||
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
|
||||
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
|
||||
|
||||
virtual MachineBasicBlock *
|
||||
MachineBasicBlock *
|
||||
EmitInstrWithCustomInserter(MachineInstr *MI,
|
||||
MachineBasicBlock *MBB) const;
|
||||
MachineBasicBlock *MBB) const override;
|
||||
|
||||
virtual void
|
||||
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
|
||||
void AdjustInstrPostInstrSelection(MachineInstr *MI,
|
||||
SDNode *Node) const override;
|
||||
|
||||
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
|
||||
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
|
||||
|
||||
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
|
||||
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
|
||||
|
||||
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
|
||||
/// unaligned memory accesses of the specified type. Returns whether it
|
||||
/// is "fast" by reference in the second argument.
|
||||
virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
|
||||
bool *Fast) const;
|
||||
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
|
||||
bool *Fast) const override;
|
||||
|
||||
virtual EVT getOptimalMemOpType(uint64_t Size,
|
||||
unsigned DstAlign, unsigned SrcAlign,
|
||||
bool IsMemset, bool ZeroMemset,
|
||||
bool MemcpyStrSrc,
|
||||
MachineFunction &MF) const;
|
||||
EVT getOptimalMemOpType(uint64_t Size,
|
||||
unsigned DstAlign, unsigned SrcAlign,
|
||||
bool IsMemset, bool ZeroMemset,
|
||||
bool MemcpyStrSrc,
|
||||
MachineFunction &MF) const override;
|
||||
|
||||
using TargetLowering::isZExtFree;
|
||||
virtual bool isZExtFree(SDValue Val, EVT VT2) const;
|
||||
bool isZExtFree(SDValue Val, EVT VT2) const override;
|
||||
|
||||
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
|
||||
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
|
||||
|
||||
|
||||
/// isLegalAddressingMode - Return true if the addressing mode represented
|
||||
/// by AM is legal for this target, for a load/store of the specified type.
|
||||
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
|
||||
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
|
||||
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
|
||||
|
||||
/// isLegalICmpImmediate - Return true if the specified immediate is legal
|
||||
/// icmp immediate, that is the target has icmp instructions which can
|
||||
/// compare a register against the immediate without having to materialize
|
||||
/// the immediate into a register.
|
||||
virtual bool isLegalICmpImmediate(int64_t Imm) const;
|
||||
bool isLegalICmpImmediate(int64_t Imm) const override;
|
||||
|
||||
/// isLegalAddImmediate - Return true if the specified immediate is legal
|
||||
/// add immediate, that is the target has add instructions which can
|
||||
/// add a register and the immediate without having to materialize
|
||||
/// the immediate into a register.
|
||||
virtual bool isLegalAddImmediate(int64_t Imm) const;
|
||||
bool isLegalAddImmediate(int64_t Imm) const override;
|
||||
|
||||
/// getPreIndexedAddressParts - returns true by value, base pointer and
|
||||
/// offset pointer and addressing mode by reference if the node's address
|
||||
/// can be legally represented as pre-indexed load / store address.
|
||||
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
|
||||
SDValue &Offset,
|
||||
ISD::MemIndexedMode &AM,
|
||||
SelectionDAG &DAG) const;
|
||||
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
|
||||
ISD::MemIndexedMode &AM,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
/// getPostIndexedAddressParts - returns true by value, base pointer and
|
||||
/// offset pointer and addressing mode by reference if this node can be
|
||||
/// combined with a load / store to form a post-indexed load / store.
|
||||
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
|
||||
SDValue &Base, SDValue &Offset,
|
||||
ISD::MemIndexedMode &AM,
|
||||
SelectionDAG &DAG) const;
|
||||
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
|
||||
SDValue &Offset, ISD::MemIndexedMode &AM,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
|
||||
APInt &KnownZero,
|
||||
APInt &KnownOne,
|
||||
const SelectionDAG &DAG,
|
||||
unsigned Depth) const;
|
||||
void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
|
||||
APInt &KnownOne,
|
||||
const SelectionDAG &DAG,
|
||||
unsigned Depth) const override;
|
||||
|
||||
|
||||
virtual bool ExpandInlineAsm(CallInst *CI) const;
|
||||
bool ExpandInlineAsm(CallInst *CI) const override;
|
||||
|
||||
ConstraintType getConstraintType(const std::string &Constraint) const;
|
||||
ConstraintType
|
||||
getConstraintType(const std::string &Constraint) const override;
|
||||
|
||||
/// Examine constraint string and operand type and determine a weight value.
|
||||
/// The operand object must already have been set up with the operand type.
|
||||
ConstraintWeight getSingleConstraintMatchWeight(
|
||||
AsmOperandInfo &info, const char *constraint) const;
|
||||
AsmOperandInfo &info, const char *constraint) const override;
|
||||
|
||||
std::pair<unsigned, const TargetRegisterClass*>
|
||||
getRegForInlineAsmConstraint(const std::string &Constraint,
|
||||
MVT VT) const;
|
||||
MVT VT) const override;
|
||||
|
||||
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
|
||||
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
|
||||
/// true it means one of the asm constraint of the inline asm instruction
|
||||
/// being processed is 'm'.
|
||||
virtual void LowerAsmOperandForConstraint(SDValue Op,
|
||||
std::string &Constraint,
|
||||
std::vector<SDValue> &Ops,
|
||||
SelectionDAG &DAG) const;
|
||||
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
|
||||
std::vector<SDValue> &Ops,
|
||||
SelectionDAG &DAG) const override;
|
||||
|
||||
const ARMSubtarget* getSubtarget() const {
|
||||
return Subtarget;
|
||||
|
@ -352,45 +349,46 @@ namespace llvm {
|
|||
|
||||
/// getRegClassFor - Return the register class that should be used for the
|
||||
/// specified value type.
|
||||
virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
|
||||
const TargetRegisterClass *getRegClassFor(MVT VT) const override;
|
||||
|
||||
/// getMaximalGlobalOffset - Returns the maximal possible offset which can
|
||||
/// be used for loads / stores from the global.
|
||||
virtual unsigned getMaximalGlobalOffset() const;
|
||||
unsigned getMaximalGlobalOffset() const override;
|
||||
|
||||
/// Returns true if a cast between SrcAS and DestAS is a noop.
|
||||
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
|
||||
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
|
||||
// Addrspacecasts are always noops.
|
||||
return true;
|
||||
}
|
||||
|
||||
/// createFastISel - This method returns a target specific FastISel object,
|
||||
/// or null if the target does not support "fast" ISel.
|
||||
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo) const;
|
||||
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo) const override;
|
||||
|
||||
Sched::Preference getSchedulingPreference(SDNode *N) const;
|
||||
Sched::Preference getSchedulingPreference(SDNode *N) const override;
|
||||
|
||||
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
|
||||
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
|
||||
bool
|
||||
isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
|
||||
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
|
||||
|
||||
/// isFPImmLegal - Returns true if the target can instruction select the
|
||||
/// specified FP immediate natively. If false, the legalizer will
|
||||
/// materialize the FP immediate as a load from a constant pool.
|
||||
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
|
||||
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
|
||||
|
||||
virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
|
||||
const CallInst &I,
|
||||
unsigned Intrinsic) const;
|
||||
bool getTgtMemIntrinsic(IntrinsicInfo &Info,
|
||||
const CallInst &I,
|
||||
unsigned Intrinsic) const override;
|
||||
|
||||
/// \brief Returns true if it is beneficial to convert a load of a constant
|
||||
/// to just the constant itself.
|
||||
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
||||
Type *Ty) const;
|
||||
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
|
||||
Type *Ty) const override;
|
||||
|
||||
protected:
|
||||
std::pair<const TargetRegisterClass*, uint8_t>
|
||||
findRepresentativeClass(MVT VT) const;
|
||||
findRepresentativeClass(MVT VT) const override;
|
||||
|
||||
private:
|
||||
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
|
||||
|
@ -467,7 +465,7 @@ namespace llvm {
|
|||
/// lower a pair of fmul and fadd to the latter so it's not clear that there
|
||||
/// would be a gain or that the gain would be worthwhile enough to risk
|
||||
/// correctness bugs.
|
||||
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
|
||||
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
|
||||
|
||||
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
|
||||
|
||||
|
@ -478,12 +476,12 @@ namespace llvm {
|
|||
SmallVectorImpl<SDValue> &InVals,
|
||||
bool isThisReturn, SDValue ThisVal) const;
|
||||
|
||||
virtual SDValue
|
||||
SDValue
|
||||
LowerFormalArguments(SDValue Chain,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
SDLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
SmallVectorImpl<SDValue> &InVals) const override;
|
||||
|
||||
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
|
||||
SDLoc dl, SDValue &Chain,
|
||||
|
@ -494,12 +492,12 @@ namespace llvm {
|
|||
unsigned ArgSize,
|
||||
bool ForceMutable,
|
||||
unsigned ByValStoreOffset,
|
||||
unsigned TotalArgRegsSaveSize) const;
|
||||
unsigned TotalArgRegsSaveSize) const;
|
||||
|
||||
void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
|
||||
SDLoc dl, SDValue &Chain,
|
||||
unsigned ArgOffset,
|
||||
unsigned TotalArgRegsSaveSize,
|
||||
unsigned TotalArgRegsSaveSize,
|
||||
bool ForceMutable = false) const;
|
||||
|
||||
void computeRegArea(CCState &CCInfo, MachineFunction &MF,
|
||||
|
@ -508,12 +506,12 @@ namespace llvm {
|
|||
unsigned &ArgRegsSize,
|
||||
unsigned &ArgRegsSaveSize) const;
|
||||
|
||||
virtual SDValue
|
||||
SDValue
|
||||
LowerCall(TargetLowering::CallLoweringInfo &CLI,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
SmallVectorImpl<SDValue> &InVals) const override;
|
||||
|
||||
/// HandleByVal - Target-specific cleanup for ByVal support.
|
||||
virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
|
||||
void HandleByVal(CCState *, unsigned &, unsigned) const override;
|
||||
|
||||
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
|
||||
/// for tail call optimization. Targets which want to do tail call
|
||||
|
@ -528,21 +526,21 @@ namespace llvm {
|
|||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
SelectionDAG& DAG) const;
|
||||
|
||||
virtual bool CanLowerReturn(CallingConv::ID CallConv,
|
||||
MachineFunction &MF, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
LLVMContext &Context) const;
|
||||
bool CanLowerReturn(CallingConv::ID CallConv,
|
||||
MachineFunction &MF, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
LLVMContext &Context) const override;
|
||||
|
||||
virtual SDValue
|
||||
SDValue
|
||||
LowerReturn(SDValue Chain,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
SDLoc dl, SelectionDAG &DAG) const;
|
||||
SDLoc dl, SelectionDAG &DAG) const override;
|
||||
|
||||
virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
|
||||
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
|
||||
|
||||
virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
|
||||
bool mayBeEmittedAsTailCall(CallInst *CI) const override;
|
||||
|
||||
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
|
||||
SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
|
||||
|
|
|
@ -97,7 +97,7 @@ namespace {
|
|||
static char ID;
|
||||
ARMCGBR() : MachineFunctionPass(ID) {}
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &MF) {
|
||||
bool runOnMachineFunction(MachineFunction &MF) override {
|
||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||
if (AFI->getGlobalBaseReg() == 0)
|
||||
return false;
|
||||
|
@ -146,11 +146,11 @@ namespace {
|
|||
return true;
|
||||
}
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM PIC Global Base Reg Initialization";
|
||||
}
|
||||
|
||||
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.setPreservesCFG();
|
||||
MachineFunctionPass::getAnalysisUsage(AU);
|
||||
}
|
||||
|
|
|
@ -28,17 +28,17 @@ public:
|
|||
explicit ARMInstrInfo(const ARMSubtarget &STI);
|
||||
|
||||
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const;
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const override;
|
||||
|
||||
// Return the non-pre/post incrementing version of 'Opc'. Return 0
|
||||
// if there is not such an opcode.
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const;
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const override;
|
||||
|
||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||
/// such, whenever a client has an instance of instruction info, it should
|
||||
/// always be able to get register info as well (through this method).
|
||||
///
|
||||
const ARMRegisterInfo &getRegisterInfo() const { return RI; }
|
||||
const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
@ -53,45 +53,45 @@ namespace llvm {
|
|||
/// overwriting OLD with a branch to NEW. This is used for self-modifying
|
||||
/// code.
|
||||
///
|
||||
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
||||
void replaceMachineCodeForFunction(void *Old, void *New) override;
|
||||
|
||||
/// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter object
|
||||
/// to emit an indirect symbol which contains the address of the specified
|
||||
/// ptr.
|
||||
virtual void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
|
||||
JITCodeEmitter &JCE);
|
||||
void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
|
||||
JITCodeEmitter &JCE) override;
|
||||
|
||||
// getStubLayout - Returns the size and alignment of the largest call stub
|
||||
// on ARM.
|
||||
virtual StubLayout getStubLayout();
|
||||
StubLayout getStubLayout() override;
|
||||
|
||||
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
|
||||
/// small native function that simply calls the function at the specified
|
||||
/// address.
|
||||
virtual void *emitFunctionStub(const Function* F, void *Fn,
|
||||
JITCodeEmitter &JCE);
|
||||
void *emitFunctionStub(const Function* F, void *Fn,
|
||||
JITCodeEmitter &JCE) override;
|
||||
|
||||
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
|
||||
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
|
||||
LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
|
||||
|
||||
/// relocate - Before the JIT can run a block of code that has been emitted,
|
||||
/// it must rewrite the code to contain the actual addresses of any
|
||||
/// referenced global symbols.
|
||||
virtual void relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char* GOTBase);
|
||||
void relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char* GOTBase) override;
|
||||
|
||||
/// hasCustomConstantPool - Allows a target to specify that constant
|
||||
/// pool address resolution is handled by the target.
|
||||
virtual bool hasCustomConstantPool() const { return true; }
|
||||
bool hasCustomConstantPool() const override { return true; }
|
||||
|
||||
/// hasCustomJumpTables - Allows a target to specify that jumptables
|
||||
/// are emitted by the target.
|
||||
virtual bool hasCustomJumpTables() const { return true; }
|
||||
bool hasCustomJumpTables() const override { return true; }
|
||||
|
||||
/// allocateSeparateGVMemory - If true, globals should be placed in
|
||||
/// separately allocated heap memory rather than in the same
|
||||
/// code memory allocated by JITCodeEmitter.
|
||||
virtual bool allocateSeparateGVMemory() const {
|
||||
bool allocateSeparateGVMemory() const override {
|
||||
#ifdef __APPLE__
|
||||
return true;
|
||||
#else
|
||||
|
|
|
@ -69,9 +69,9 @@ namespace {
|
|||
RegScavenger *RS;
|
||||
bool isThumb2;
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM load / store optimization pass";
|
||||
}
|
||||
|
||||
|
@ -1550,9 +1550,9 @@ namespace {
|
|||
MachineRegisterInfo *MRI;
|
||||
MachineFunction *MF;
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM pre- register allocation load / store optimization pass";
|
||||
}
|
||||
|
||||
|
|
|
@ -44,23 +44,21 @@ public:
|
|||
explicit ARMSelectionDAGInfo(const TargetMachine &TM);
|
||||
~ARMSelectionDAGInfo();
|
||||
|
||||
virtual
|
||||
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
|
||||
SDValue Chain,
|
||||
SDValue Dst, SDValue Src,
|
||||
SDValue Size, unsigned Align,
|
||||
bool isVolatile, bool AlwaysInline,
|
||||
MachinePointerInfo DstPtrInfo,
|
||||
MachinePointerInfo SrcPtrInfo) const;
|
||||
MachinePointerInfo SrcPtrInfo) const override;
|
||||
|
||||
// Adjust parameters for memset, see RTABI section 4.3.4
|
||||
virtual
|
||||
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
|
||||
SDValue Chain,
|
||||
SDValue Op1, SDValue Op2,
|
||||
SDValue Op3, unsigned Align,
|
||||
bool isVolatile,
|
||||
MachinePointerInfo DstPtrInfo) const;
|
||||
MachinePointerInfo DstPtrInfo) const override;
|
||||
};
|
||||
|
||||
}
|
||||
|
|
|
@ -240,7 +240,7 @@ protected:
|
|||
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
||||
|
||||
/// \brief Reset the features for the ARM target.
|
||||
virtual void resetSubtargetFeatures(const MachineFunction *MF);
|
||||
void resetSubtargetFeatures(const MachineFunction *MF) override;
|
||||
private:
|
||||
void initializeEnvironment();
|
||||
void resetSubtargetFeatures(StringRef CPU, StringRef FS);
|
||||
|
@ -384,7 +384,7 @@ public:
|
|||
/// enablePostRAScheduler - True at 'More' optimization.
|
||||
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
|
||||
TargetSubtargetInfo::AntiDepBreakMode& Mode,
|
||||
RegClassVector& CriticalPathRCs) const;
|
||||
RegClassVector& CriticalPathRCs) const override;
|
||||
|
||||
/// getInstrItins - Return the instruction itineraies based on subtarget
|
||||
/// selection.
|
||||
|
|
|
@ -166,11 +166,11 @@ public:
|
|||
return *getARMTargetMachine().getSubtargetImpl();
|
||||
}
|
||||
|
||||
virtual bool addPreISel();
|
||||
virtual bool addInstSelector();
|
||||
virtual bool addPreRegAlloc();
|
||||
virtual bool addPreSched2();
|
||||
virtual bool addPreEmitPass();
|
||||
bool addPreISel() override;
|
||||
bool addInstSelector() override;
|
||||
bool addPreRegAlloc() override;
|
||||
bool addPreSched2() override;
|
||||
bool addPreEmitPass() override;
|
||||
};
|
||||
} // namespace
|
||||
|
||||
|
|
|
@ -44,23 +44,23 @@ public:
|
|||
Reloc::Model RM, CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL);
|
||||
|
||||
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
|
||||
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
|
||||
virtual const ARMTargetLowering *getTargetLowering() const {
|
||||
ARMJITInfo *getJITInfo() override { return &JITInfo; }
|
||||
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
|
||||
const ARMTargetLowering *getTargetLowering() const override {
|
||||
// Implemented by derived classes
|
||||
llvm_unreachable("getTargetLowering not implemented");
|
||||
}
|
||||
virtual const InstrItineraryData *getInstrItineraryData() const {
|
||||
const InstrItineraryData *getInstrItineraryData() const override {
|
||||
return &InstrItins;
|
||||
}
|
||||
|
||||
/// \brief Register ARM analysis passes with a pass manager.
|
||||
virtual void addAnalysisPasses(PassManagerBase &PM);
|
||||
void addAnalysisPasses(PassManagerBase &PM) override;
|
||||
|
||||
// Pass Pipeline Configuration
|
||||
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
||||
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
||||
|
||||
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
|
||||
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
|
||||
};
|
||||
|
||||
/// ARMTargetMachine - ARM target machine.
|
||||
|
@ -79,22 +79,22 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
|
|||
Reloc::Model RM, CodeModel::Model CM,
|
||||
CodeGenOpt::Level OL);
|
||||
|
||||
virtual const ARMRegisterInfo *getRegisterInfo() const {
|
||||
const ARMRegisterInfo *getRegisterInfo() const override {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
|
||||
virtual const ARMTargetLowering *getTargetLowering() const {
|
||||
const ARMTargetLowering *getTargetLowering() const override {
|
||||
return &TLInfo;
|
||||
}
|
||||
|
||||
virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
|
||||
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
|
||||
return &TSInfo;
|
||||
}
|
||||
virtual const ARMFrameLowering *getFrameLowering() const {
|
||||
const ARMFrameLowering *getFrameLowering() const override {
|
||||
return &FrameLowering;
|
||||
}
|
||||
virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
|
||||
virtual const DataLayout *getDataLayout() const { return &DL; }
|
||||
const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
|
||||
const DataLayout *getDataLayout() const override { return &DL; }
|
||||
};
|
||||
|
||||
/// ThumbTargetMachine - Thumb target machine.
|
||||
|
@ -118,27 +118,27 @@ public:
|
|||
CodeGenOpt::Level OL);
|
||||
|
||||
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
|
||||
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
|
||||
const ARMBaseRegisterInfo *getRegisterInfo() const override {
|
||||
return &InstrInfo->getRegisterInfo();
|
||||
}
|
||||
|
||||
virtual const ARMTargetLowering *getTargetLowering() const {
|
||||
const ARMTargetLowering *getTargetLowering() const override {
|
||||
return &TLInfo;
|
||||
}
|
||||
|
||||
virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
|
||||
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
|
||||
return &TSInfo;
|
||||
}
|
||||
|
||||
/// returns either Thumb1InstrInfo or Thumb2InstrInfo
|
||||
virtual const ARMBaseInstrInfo *getInstrInfo() const {
|
||||
const ARMBaseInstrInfo *getInstrInfo() const override {
|
||||
return InstrInfo.get();
|
||||
}
|
||||
/// returns either Thumb1FrameLowering or ARMFrameLowering
|
||||
virtual const ARMFrameLowering *getFrameLowering() const {
|
||||
const ARMFrameLowering *getFrameLowering() const override {
|
||||
return FrameLowering.get();
|
||||
}
|
||||
virtual const DataLayout *getDataLayout() const { return &DL; }
|
||||
const DataLayout *getDataLayout() const override { return &DL; }
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
|
|
@ -52,7 +52,7 @@ public:
|
|||
initializeARMTTIPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
virtual void initializePass() override {
|
||||
void initializePass() override {
|
||||
pushTTIStack(this);
|
||||
}
|
||||
|
||||
|
@ -60,7 +60,7 @@ public:
|
|||
popTTIStack();
|
||||
}
|
||||
|
||||
virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
TargetTransformInfo::getAnalysisUsage(AU);
|
||||
}
|
||||
|
||||
|
@ -68,7 +68,7 @@ public:
|
|||
static char ID;
|
||||
|
||||
/// Provide necessary pointer adjustments for the two base classes.
|
||||
virtual void *getAdjustedAnalysisPointer(const void *ID) override {
|
||||
void *getAdjustedAnalysisPointer(const void *ID) override {
|
||||
if (ID == &TargetTransformInfo::ID)
|
||||
return (TargetTransformInfo*)this;
|
||||
return this;
|
||||
|
@ -77,8 +77,7 @@ public:
|
|||
/// \name Scalar TTI Implementations
|
||||
/// @{
|
||||
using TargetTransformInfo::getIntImmCost;
|
||||
virtual unsigned
|
||||
getIntImmCost(const APInt &Imm, Type *Ty) const override;
|
||||
unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
|
||||
|
||||
/// @}
|
||||
|
||||
|
@ -86,7 +85,7 @@ public:
|
|||
/// \name Vector TTI Implementations
|
||||
/// @{
|
||||
|
||||
unsigned getNumberOfRegisters(bool Vector) const {
|
||||
unsigned getNumberOfRegisters(bool Vector) const override {
|
||||
if (Vector) {
|
||||
if (ST->hasNEON())
|
||||
return 16;
|
||||
|
@ -98,7 +97,7 @@ public:
|
|||
return 13;
|
||||
}
|
||||
|
||||
unsigned getRegisterBitWidth(bool Vector) const {
|
||||
unsigned getRegisterBitWidth(bool Vector) const override {
|
||||
if (Vector) {
|
||||
if (ST->hasNEON())
|
||||
return 128;
|
||||
|
@ -108,7 +107,7 @@ public:
|
|||
return 32;
|
||||
}
|
||||
|
||||
unsigned getMaximumUnrollFactor() const {
|
||||
unsigned getMaximumUnrollFactor() const override {
|
||||
// These are out of order CPUs:
|
||||
if (ST->isCortexA15() || ST->isSwift())
|
||||
return 2;
|
||||
|
@ -116,23 +115,27 @@ public:
|
|||
}
|
||||
|
||||
unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
|
||||
int Index, Type *SubTp) const;
|
||||
int Index, Type *SubTp) const override;
|
||||
|
||||
unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
|
||||
Type *Src) const;
|
||||
Type *Src) const override;
|
||||
|
||||
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
|
||||
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
|
||||
Type *CondTy) const override;
|
||||
|
||||
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
|
||||
unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
|
||||
unsigned Index) const override;
|
||||
|
||||
unsigned getAddressComputationCost(Type *Val, bool IsComplex) const;
|
||||
unsigned getAddressComputationCost(Type *Val,
|
||||
bool IsComplex) const override;
|
||||
|
||||
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
|
||||
OperandValueKind Op1Info = OK_AnyValue,
|
||||
OperandValueKind Op2Info = OK_AnyValue) const;
|
||||
unsigned
|
||||
getArithmeticInstrCost(unsigned Opcode, Type *Ty,
|
||||
OperandValueKind Op1Info = OK_AnyValue,
|
||||
OperandValueKind Op2Info = OK_AnyValue) const override;
|
||||
|
||||
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
|
||||
unsigned AddressSpace) const;
|
||||
unsigned AddressSpace) const override;
|
||||
/// @}
|
||||
};
|
||||
|
||||
|
|
|
@ -26,8 +26,8 @@ public:
|
|||
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
|
||||
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
|
||||
|
||||
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
|
||||
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
|
||||
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
|
||||
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
|
||||
|
||||
// Autogenerated by tblgen.
|
||||
void printInstruction(const MCInst *MI, raw_ostream &O);
|
||||
|
|
|
@ -56,16 +56,16 @@ public:
|
|||
|
||||
/// @}
|
||||
|
||||
void PrintImpl(raw_ostream &OS) const;
|
||||
void PrintImpl(raw_ostream &OS) const override;
|
||||
bool EvaluateAsRelocatableImpl(MCValue &Res,
|
||||
const MCAsmLayout *Layout) const;
|
||||
void AddValueSymbols(MCAssembler *) const;
|
||||
const MCSection *FindAssociatedSection() const {
|
||||
const MCAsmLayout *Layout) const override;
|
||||
void AddValueSymbols(MCAssembler *) const override;
|
||||
const MCSection *FindAssociatedSection() const override {
|
||||
return getSubExpr()->FindAssociatedSection();
|
||||
}
|
||||
|
||||
// There are no TLS ARMMCExprs at the moment.
|
||||
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
|
||||
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
|
||||
|
||||
static bool classof(const MCExpr *E) {
|
||||
return E->getKind() == MCExpr::Target;
|
||||
|
|
|
@ -40,9 +40,9 @@ namespace {
|
|||
static char ID;
|
||||
MLxExpansion() : MachineFunctionPass(ID) {}
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "ARM MLA / MLS expansion pass";
|
||||
}
|
||||
|
||||
|
|
|
@ -32,23 +32,24 @@ public:
|
|||
|
||||
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
|
||||
/// the function.
|
||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
void emitPrologue(MachineFunction &MF) const override;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
|
||||
|
||||
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
MachineBasicBlock::iterator MI,
|
||||
const std::vector<CalleeSavedInfo> &CSI,
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const;
|
||||
bool hasReservedCallFrame(const MachineFunction &MF) const override;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const;
|
||||
void
|
||||
eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MI) const override;
|
||||
};
|
||||
|
||||
} // End llvm namespace
|
||||
|
|
|
@ -27,33 +27,33 @@ public:
|
|||
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
|
||||
|
||||
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const;
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const override;
|
||||
|
||||
// Return the non-pre/post incrementing version of 'Opc'. Return 0
|
||||
// if there is not such an opcode.
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const;
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const override;
|
||||
|
||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||
/// such, whenever a client has an instance of instruction info, it should
|
||||
/// always be able to get register info as well (through this method).
|
||||
///
|
||||
const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
|
||||
const Thumb1RegisterInfo &getRegisterInfo() const override { return RI; }
|
||||
|
||||
void copyPhysReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I, DebugLoc DL,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
bool KillSrc) const;
|
||||
bool KillSrc) const override;
|
||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
};
|
||||
}
|
||||
|
|
|
@ -27,21 +27,20 @@ struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
|
|||
public:
|
||||
Thumb1RegisterInfo(const ARMSubtarget &STI);
|
||||
|
||||
const TargetRegisterClass*
|
||||
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
|
||||
const TargetRegisterClass *
|
||||
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
|
||||
|
||||
const TargetRegisterClass*
|
||||
getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
|
||||
const TargetRegisterClass *
|
||||
getPointerRegClass(const MachineFunction &MF,
|
||||
unsigned Kind = 0) const override;
|
||||
|
||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||
/// specified immediate.
|
||||
void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MBBI,
|
||||
DebugLoc dl,
|
||||
unsigned DestReg, unsigned SubIdx, int Val,
|
||||
ARMCC::CondCodes Pred = ARMCC::AL,
|
||||
unsigned PredReg = 0,
|
||||
unsigned MIFlags = MachineInstr::NoFlags) const;
|
||||
void
|
||||
emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
||||
DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
||||
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
||||
unsigned MIFlags = MachineInstr::NoFlags) const override;
|
||||
|
||||
// rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
|
||||
// however much remains to be handled. Return 'true' if no further
|
||||
|
@ -50,15 +49,15 @@ public:
|
|||
unsigned FrameReg, int &Offset,
|
||||
const ARMBaseInstrInfo &TII) const;
|
||||
void resolveFrameIndex(MachineBasicBlock::iterator I,
|
||||
unsigned BaseReg, int64_t Offset) const;
|
||||
unsigned BaseReg, int64_t Offset) const override;
|
||||
bool saveScavengerRegister(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I,
|
||||
MachineBasicBlock::iterator &UseMI,
|
||||
const TargetRegisterClass *RC,
|
||||
unsigned Reg) const;
|
||||
unsigned Reg) const override;
|
||||
void eliminateFrameIndex(MachineBasicBlock::iterator II,
|
||||
int SPAdj, unsigned FIOperandNum,
|
||||
RegScavenger *RS = NULL) const;
|
||||
RegScavenger *RS = NULL) const override;
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
@ -33,9 +33,9 @@ namespace {
|
|||
const TargetRegisterInfo *TRI;
|
||||
ARMFunctionInfo *AFI;
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &Fn);
|
||||
bool runOnMachineFunction(MachineFunction &Fn) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "Thumb IT blocks insertion pass";
|
||||
}
|
||||
|
||||
|
|
|
@ -28,40 +28,40 @@ public:
|
|||
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
|
||||
|
||||
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const;
|
||||
void getNoopForMachoTarget(MCInst &NopInst) const override;
|
||||
|
||||
// Return the non-pre/post incrementing version of 'Opc'. Return 0
|
||||
// if there is not such an opcode.
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const;
|
||||
unsigned getUnindexedOpcode(unsigned Opc) const override;
|
||||
|
||||
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
|
||||
MachineBasicBlock *NewDest) const;
|
||||
MachineBasicBlock *NewDest) const override;
|
||||
|
||||
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI) const;
|
||||
MachineBasicBlock::iterator MBBI) const override;
|
||||
|
||||
void copyPhysReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I, DebugLoc DL,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
bool KillSrc) const;
|
||||
bool KillSrc) const override;
|
||||
|
||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC,
|
||||
const TargetRegisterInfo *TRI) const;
|
||||
const TargetRegisterInfo *TRI) const override;
|
||||
|
||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||
/// such, whenever a client has an instance of instruction info, it should
|
||||
/// always be able to get register info as well (through this method).
|
||||
///
|
||||
const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
|
||||
const Thumb2RegisterInfo &getRegisterInfo() const override { return RI; }
|
||||
};
|
||||
|
||||
/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
|
||||
|
|
|
@ -29,13 +29,11 @@ public:
|
|||
|
||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||
/// specified immediate.
|
||||
void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator &MBBI,
|
||||
DebugLoc dl,
|
||||
unsigned DestReg, unsigned SubIdx, int Val,
|
||||
ARMCC::CondCodes Pred = ARMCC::AL,
|
||||
unsigned PredReg = 0,
|
||||
unsigned MIFlags = MachineInstr::NoFlags) const;
|
||||
void
|
||||
emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
||||
DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
|
||||
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
||||
unsigned MIFlags = MachineInstr::NoFlags) const override;
|
||||
};
|
||||
}
|
||||
|
||||
|
|
|
@ -137,9 +137,9 @@ namespace {
|
|||
const Thumb2InstrInfo *TII;
|
||||
const ARMSubtarget *STI;
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &MF);
|
||||
bool runOnMachineFunction(MachineFunction &MF) override;
|
||||
|
||||
virtual const char *getPassName() const {
|
||||
const char *getPassName() const override {
|
||||
return "Thumb2 instruction size reduction pass";
|
||||
}
|
||||
|
||||
|
|
Loading…
Reference in New Issue