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[C++11] Add 'override' keyword to virtual methods that override their base class. 

llvm-svn: 203433
This commit is contained in:
Craig Topper 2014-03-10 02:09:33 +00:00
parent 245b7fd3f2
commit 6bc27bf359
31 changed files with 402 additions and 409 deletions
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4
llvm/lib/Target/ARM/A15SDOptimizer.cpp
View File

@ -49,9 +49,9 @@ namespace {
static char ID;
A15SDOptimizer() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM A15 S->D optimizer";
}

212
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -42,37 +42,37 @@ public:
// if there is not such an opcode.
virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const;
MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
MachineBasicBlock::iterator &MBBI,
LiveVariables *LV) const override;
virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
const ARMSubtarget &getSubtarget() const { return Subtarget; }
ScheduleHazardRecognizer *
CreateTargetHazardRecognizer(const TargetMachine *TM,
const ScheduleDAG *DAG) const;
const ScheduleDAG *DAG) const override;
ScheduleHazardRecognizer *
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
const ScheduleDAG *DAG) const;
const ScheduleDAG *DAG) const override;
// Branch analysis.
virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const;
bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify = false) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override;
virtual
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
// Predication support.
bool isPredicated(const MachineInstr *MI) const;
bool isPredicated(const MachineInstr *MI) const override;
ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
@ -80,76 +80,73 @@ public:
: ARMCC::AL;
}
virtual
bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Pred) const;
const SmallVectorImpl<MachineOperand> &Pred) const override;
virtual
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const;
const SmallVectorImpl<MachineOperand> &Pred2) const override;
virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const;
bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override;
virtual bool isPredicable(MachineInstr *MI) const;
bool isPredicable(MachineInstr *MI) const override;
/// GetInstSize - Returns the size of the specified MachineInstr.
///
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const;
virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const;
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
int &FrameIndex) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
DebugLoc DL, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
const TargetRegisterInfo &TRI) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig,
const TargetRegisterInfo &TRI) const override;
MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
MachineInstr *duplicate(MachineInstr *Orig,
MachineFunction &MF) const override;
MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
MachineInstr *commuteInstruction(MachineInstr*,
bool=false) const override;
const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
unsigned SubIdx, unsigned State,
const TargetRegisterInfo *TRI) const;
virtual bool produceSameValue(const MachineInstr *MI0,
const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const;
bool produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1,
const MachineRegisterInfo *MRI) const override;
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
/// determine if two loads are loading from the same base address. It should
/// only return true if the base pointers are the same and the only
/// differences between the two addresses is the offset. It also returns the
/// offsets by reference.
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
int64_t &Offset1, int64_t &Offset2)const;
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
int64_t &Offset2) const override;
/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
@ -159,83 +156,79 @@ public:
/// from the common base address. It returns true if it decides it's desirable
/// to schedule the two loads together. "NumLoads" is the number of loads that
/// have already been scheduled after Load1.
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const;
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
int64_t Offset1, int64_t Offset2,
unsigned NumLoads) const override;
virtual bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const;
bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
unsigned NumCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const;
bool isProfitableToIfCvt(MachineBasicBlock &MBB,
unsigned NumCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const override;
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumT, unsigned ExtraT,
MachineBasicBlock &FMBB,
unsigned NumF, unsigned ExtraF,
const BranchProbability &Probability) const;
bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
unsigned ExtraT, MachineBasicBlock &FMBB,
unsigned NumF, unsigned ExtraF,
const BranchProbability &Probability) const override;
virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
unsigned NumCycles,
const BranchProbability
&Probability) const {
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
const BranchProbability &Probability) const override {
return NumCycles == 1;
}
virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const;
bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
MachineBasicBlock &FMBB) const override;
/// analyzeCompare - For a comparison instruction, return the source registers
/// in SrcReg and SrcReg2 if having two register operands, and the value it
/// compares against in CmpValue. Return true if the comparison instruction
/// can be analyzed.
virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
unsigned &SrcReg2, int &CmpMask,
int &CmpValue) const;
bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
unsigned &SrcReg2, int &CmpMask,
int &CmpValue) const override;
/// optimizeCompareInstr - Convert the instruction to set the zero flag so
/// that we can remove a "comparison with zero"; Remove a redundant CMP
/// instruction if the flags can be updated in the same way by an earlier
/// instruction such as SUB.
virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI) const;
bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
unsigned SrcReg2, int CmpMask, int CmpValue,
const MachineRegisterInfo *MRI) const override;
virtual bool analyzeSelect(const MachineInstr *MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const;
bool analyzeSelect(const MachineInstr *MI,
SmallVectorImpl<MachineOperand> &Cond,
unsigned &TrueOp, unsigned &FalseOp,
bool &Optimizable) const override;
virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
MachineInstr *optimizeSelect(MachineInstr *MI, bool) const override;
/// FoldImmediate - 'Reg' is known to be defined by a move immediate
/// instruction, try to fold the immediate into the use instruction.
virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const;
bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
unsigned Reg, MachineRegisterInfo *MRI) const override;
virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const;
unsigned getNumMicroOps(const InstrItineraryData *ItinData,
const MachineInstr *MI) const override;
virtual
int getOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const;
virtual
const MachineInstr *UseMI,
unsigned UseIdx) const override;
int getOperandLatency(const InstrItineraryData *ItinData,
SDNode *DefNode, unsigned DefIdx,
SDNode *UseNode, unsigned UseIdx) const;
SDNode *UseNode, unsigned UseIdx) const override;
/// VFP/NEON execution domains.
std::pair<uint16_t, uint16_t>
getExecutionDomain(const MachineInstr *MI) const;
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
getExecutionDomain(const MachineInstr *MI) const override;
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
const TargetRegisterInfo*) const;
const TargetRegisterInfo*) const override;
void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
/// Get the number of addresses by LDM or VLDM or zero for unknown.
unsigned getNumLDMAddresses(const MachineInstr *MI) const;
@ -264,24 +257,27 @@ private:
const MCInstrDesc &UseMCID,
unsigned UseIdx, unsigned UseAlign) const;
unsigned getPredicationCost(const MachineInstr *MI) const;
unsigned getPredicationCost(const MachineInstr *MI) const override;
unsigned getInstrLatency(const InstrItineraryData *ItinData,
const MachineInstr *MI,
unsigned *PredCost = 0) const;
unsigned *PredCost = 0) const override;
int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const;
SDNode *Node) const override;
bool hasHighOperandLatency(const InstrItineraryData *ItinData,
const MachineRegisterInfo *MRI,
const MachineInstr *DefMI, unsigned DefIdx,
const MachineInstr *UseMI, unsigned UseIdx) const;
const MachineInstr *UseMI,
unsigned UseIdx) const override;
bool hasLowDefLatency(const InstrItineraryData *ItinData,
const MachineInstr *DefMI, unsigned DefIdx) const;
const MachineInstr *DefMI,
unsigned DefIdx) const override;
/// verifyInstruction - Perform target specific instruction verification.
bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
bool verifyInstruction(const MachineInstr *MI,
StringRef &ErrInfo) const override;
private:
/// Modeling special VFP / NEON fp MLA / MLS hazards.

68
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -100,8 +100,9 @@ protected:
public:
/// Code Generation virtual methods...
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
const uint32_t *getCallPreservedMask(CallingConv::ID) const;
const uint16_t *
getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
const uint32_t *getNoPreservedMask() const;
/// getThisReturnPreservedMask - Returns a call preserved mask specific to the
@ -113,48 +114,51 @@ public:
/// Should return NULL in the case that the calling convention does not have
/// this property
const uint32_t *getThisReturnPreservedMask(CallingConv::ID) const;
BitVector getReservedRegs(const MachineFunction &MF) const;
const TargetRegisterClass*
getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
const TargetRegisterClass*
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const override;
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const;
MachineFunction &MF) const override;
void getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF,
const VirtRegMap *VRM) const;
const VirtRegMap *VRM) const override;
void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const;
MachineFunction &MF) const override;
virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const override;
bool hasBasePointer(const MachineFunction &MF) const;
bool canRealignStack(const MachineFunction &MF) const;
bool needsStackRealignment(const MachineFunction &MF) const;
int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const;
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
bool needsStackRealignment(const MachineFunction &MF) const override;
int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
int Idx) const override;
bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
void materializeFrameBaseRegister(MachineBasicBlock *MBB,
unsigned BaseReg, int FrameIdx,
int64_t Offset) const;
int64_t Offset) const override;
void resolveFrameIndex(MachineBasicBlock::iterator I,
unsigned BaseReg, int64_t Offset) const;
bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
unsigned BaseReg, int64_t Offset) const override;
bool isFrameOffsetLegal(const MachineInstr *MI,
int64_t Offset) const override;
bool cannotEliminateFrame(const MachineFunction &MF) const;
// Debug information queries.
unsigned getFrameRegister(const MachineFunction &MF) const;
unsigned getFrameRegister(const MachineFunction &MF) const override;
unsigned getBaseRegister() const { return BasePtr; }
bool isLowRegister(unsigned Reg) const;
@ -164,27 +168,25 @@ public:
/// specified immediate.
virtual void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
DebugLoc dl,
unsigned DestReg, unsigned SubIdx,
int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
DebugLoc dl, unsigned DestReg, unsigned SubIdx,
int Val, ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0,
unsigned MIFlags = MachineInstr::NoFlags)const;
/// Code Generation virtual methods...
virtual bool mayOverrideLocalAssignment() const;
bool mayOverrideLocalAssignment() const override;
virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const;
bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const override;
};
} // end namespace llvm

6
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -57,7 +57,7 @@ namespace {
bool IsPIC;
bool IsThumb;
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineModuleInfo>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@ -76,9 +76,9 @@ namespace {
/// machine instructions.
uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM Machine Code Emitter";
}

4
llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -266,9 +266,9 @@ namespace {
static char ID;
ARMConstantIslands() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM constant island placement and branch shortening pass";
}

40
llvm/lib/Target/ARM/ARMConstantPoolValue.h
View File

@ -103,12 +103,12 @@ public:
bool isLSDA() const { return Kind == ARMCP::CPLSDA; }
bool isMachineBasicBlock() const{ return Kind == ARMCP::CPMachineBasicBlock; }
virtual unsigned getRelocationInfo() const { return 2; }
unsigned getRelocationInfo() const override { return 2; }
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment);
int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment) override;
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
/// hasSameValue - Return true if this ARM constpool value can share the same
/// constantpool entry as another ARM constpool value.
@ -120,7 +120,7 @@ public:
this->Modifier == A->Modifier;
}
virtual void print(raw_ostream &O) const;
void print(raw_ostream &O) const override;
void print(raw_ostream *O) const { if (O) print(*O); }
void dump() const;
};
@ -164,16 +164,16 @@ public:
const GlobalValue *getGV() const;
const BlockAddress *getBlockAddress() const;
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment);
int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment) override;
/// hasSameValue - Return true if this ARM constpool value can share the same
/// constantpool entry as another ARM constpool value.
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
virtual void print(raw_ostream &O) const;
void print(raw_ostream &O) const override;
static bool classof(const ARMConstantPoolValue *APV) {
return APV->isGlobalValue() || APV->isBlockAddress() || APV->isLSDA();
}
@ -198,16 +198,16 @@ public:
const char *getSymbol() const { return S.c_str(); }
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment);
int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment) override;
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
/// hasSameValue - Return true if this ARM constpool value can share the same
/// constantpool entry as another ARM constpool value.
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
virtual void print(raw_ostream &O) const;
void print(raw_ostream &O) const override;
static bool classof(const ARMConstantPoolValue *ACPV) {
return ACPV->isExtSymbol();
@ -234,16 +234,16 @@ public:
const MachineBasicBlock *getMBB() const { return MBB; }
virtual int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment);
int getExistingMachineCPValue(MachineConstantPool *CP,
unsigned Alignment) override;
virtual void addSelectionDAGCSEId(FoldingSetNodeID &ID);
void addSelectionDAGCSEId(FoldingSetNodeID &ID) override;
/// hasSameValue - Return true if this ARM constpool value can share the same
/// constantpool entry as another ARM constpool value.
virtual bool hasSameValue(ARMConstantPoolValue *ACPV);
bool hasSameValue(ARMConstantPoolValue *ACPV) override;
virtual void print(raw_ostream &O) const;
void print(raw_ostream &O) const override;
static bool classof(const ARMConstantPoolValue *ACPV) {
return ACPV->isMachineBasicBlock();

4
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -46,9 +46,9 @@ namespace {
const ARMSubtarget *STI;
ARMFunctionInfo *AFI;
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM pseudo instruction expansion pass";
}

12
llvm/lib/Target/ARM/ARMFastISel.cpp
View File

@ -144,12 +144,12 @@ class ARMFastISel : public FastISel {
// Backend specific FastISel code.
private:
virtual bool TargetSelectInstruction(const Instruction *I);
virtual unsigned TargetMaterializeConstant(const Constant *C);
virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI);
virtual bool FastLowerArguments();
bool TargetSelectInstruction(const Instruction *I) override;
unsigned TargetMaterializeConstant(const Constant *C) override;
unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
const LoadInst *LI) override;
bool FastLowerArguments() override;
private:
#include "ARMGenFastISel.inc"

35
llvm/lib/Target/ARM/ARMFrameLowering.h
View File

@ -33,31 +33,30 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override;
bool hasFP(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const;
bool hasFP(const MachineFunction &MF) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
int getFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg) const;
int ResolveFrameIndexReference(const MachineFunction &MF,
int FI,
unsigned &FrameReg) const override;
int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
unsigned &FrameReg, int SPAdj) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
RegScavenger *RS) const;
RegScavenger *RS) const override;
private:
void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
@ -71,10 +70,10 @@ public:
bool(*Func)(unsigned, bool),
unsigned NumAlignedDPRCS2Regs) const;
virtual void eliminateCallFramePseudoInstr(
MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
void
eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
};
} // End llvm namespace

10
llvm/lib/Target/ARM/ARMHazardRecognizer.h
View File

@ -37,11 +37,11 @@ public:
: ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"),
LastMI(0) {}
virtual HazardType getHazardType(SUnit *SU, int Stalls);
virtual void Reset();
virtual void EmitInstruction(SUnit *SU);
virtual void AdvanceCycle();
virtual void RecedeCycle();
HazardType getHazardType(SUnit *SU, int Stalls) override;
void Reset() override;
void EmitInstruction(SUnit *SU) override;
void AdvanceCycle() override;
void RecedeCycle() override;
};
} // end namespace llvm

11
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -73,11 +73,11 @@ public:
Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM Instruction Selection";
}
virtual void PreprocessISelDAG();
void PreprocessISelDAG() override;
/// getI32Imm - Return a target constant of type i32 with the specified
/// value.
@ -85,7 +85,7 @@ public:
return CurDAG->getTargetConstant(Imm, MVT::i32);
}
SDNode *Select(SDNode *N);
SDNode *Select(SDNode *N) override;
bool hasNoVMLxHazardUse(SDNode *N) const;
@ -257,9 +257,8 @@ private:
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps);
bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
std::vector<SDValue> &OutOps) override;
// Form pairs of consecutive R, S, D, or Q registers.
SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);

152
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -234,117 +234,114 @@ namespace llvm {
public:
explicit ARMTargetLowering(TargetMachine &TM);
virtual unsigned getJumpTableEncoding() const;
unsigned getJumpTableEncoding() const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// ReplaceNodeResults - Replace the results of node with an illegal result
/// type with new values built out of custom code.
///
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const override;
virtual const char *getTargetNodeName(unsigned Opcode) const;
const char *getTargetNodeName(unsigned Opcode) const override;
virtual bool isSelectSupported(SelectSupportKind Kind) const {
bool isSelectSupported(SelectSupportKind Kind) const override {
// ARM does not support scalar condition selects on vectors.
return (Kind != ScalarCondVectorVal);
}
/// getSetCCResultType - Return the value type to use for ISD::SETCC.
virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
virtual MachineBasicBlock *
MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *MBB) const;
MachineBasicBlock *MBB) const override;
virtual void
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
void AdjustInstrPostInstrSelection(MachineInstr *MI,
SDNode *Node) const override;
SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
/// allowsUnalignedMemoryAccesses - Returns true if the target allows
/// unaligned memory accesses of the specified type. Returns whether it
/// is "fast" by reference in the second argument.
virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const;
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
bool *Fast) const override;
virtual EVT getOptimalMemOpType(uint64_t Size,
unsigned DstAlign, unsigned SrcAlign,
bool IsMemset, bool ZeroMemset,
bool MemcpyStrSrc,
MachineFunction &MF) const;
EVT getOptimalMemOpType(uint64_t Size,
unsigned DstAlign, unsigned SrcAlign,
bool IsMemset, bool ZeroMemset,
bool MemcpyStrSrc,
MachineFunction &MF) const override;
using TargetLowering::isZExtFree;
virtual bool isZExtFree(SDValue Val, EVT VT2) const;
bool isZExtFree(SDValue Val, EVT VT2) const override;
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type.
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
/// isLegalICmpImmediate - Return true if the specified immediate is legal
/// icmp immediate, that is the target has icmp instructions which can
/// compare a register against the immediate without having to materialize
/// the immediate into a register.
virtual bool isLegalICmpImmediate(int64_t Imm) const;
bool isLegalICmpImmediate(int64_t Imm) const override;
/// isLegalAddImmediate - Return true if the specified immediate is legal
/// add immediate, that is the target has add instructions which can
/// add a register and the immediate without having to materialize
/// the immediate into a register.
virtual bool isLegalAddImmediate(int64_t Imm) const;
bool isLegalAddImmediate(int64_t Imm) const override;
/// getPreIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if the node's address
/// can be legally represented as pre-indexed load / store address.
virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const;
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override;
/// getPostIndexedAddressParts - returns true by value, base pointer and
/// offset pointer and addressing mode by reference if this node can be
/// combined with a load / store to form a post-indexed load / store.
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const;
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
SDValue &Offset, ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override;
virtual void computeMaskedBitsForTargetNode(const SDValue Op,
APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth) const;
void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero,
APInt &KnownOne,
const SelectionDAG &DAG,
unsigned Depth) const override;
virtual bool ExpandInlineAsm(CallInst *CI) const;
bool ExpandInlineAsm(CallInst *CI) const override;
ConstraintType getConstraintType(const std::string &Constraint) const;
ConstraintType
getConstraintType(const std::string &Constraint) const override;
/// Examine constraint string and operand type and determine a weight value.
/// The operand object must already have been set up with the operand type.
ConstraintWeight getSingleConstraintMatchWeight(
AsmOperandInfo &info, const char *constraint) const;
AsmOperandInfo &info, const char *constraint) const override;
std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const;
MVT VT) const override;
/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
/// true it means one of the asm constraint of the inline asm instruction
/// being processed is 'm'.
virtual void LowerAsmOperandForConstraint(SDValue Op,
std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
const ARMSubtarget* getSubtarget() const {
return Subtarget;
@ -352,45 +349,46 @@ namespace llvm {
/// getRegClassFor - Return the register class that should be used for the
/// specified value type.
virtual const TargetRegisterClass *getRegClassFor(MVT VT) const;
const TargetRegisterClass *getRegClassFor(MVT VT) const override;
/// getMaximalGlobalOffset - Returns the maximal possible offset which can
/// be used for loads / stores from the global.
virtual unsigned getMaximalGlobalOffset() const;
unsigned getMaximalGlobalOffset() const override;
/// Returns true if a cast between SrcAS and DestAS is a noop.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
// Addrspacecasts are always noops.
return true;
}
/// createFastISel - This method returns a target specific FastISel object,
/// or null if the target does not support "fast" ISel.
virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const;
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
const TargetLibraryInfo *libInfo) const override;
Sched::Preference getSchedulingPreference(SDNode *N) const;
Sched::Preference getSchedulingPreference(SDNode *N) const override;
bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
bool
isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
/// isFPImmLegal - Returns true if the target can instruction select the
/// specified FP immediate natively. If false, the legalizer will
/// materialize the FP immediate as a load from a constant pool.
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
unsigned Intrinsic) const;
bool getTgtMemIntrinsic(IntrinsicInfo &Info,
const CallInst &I,
unsigned Intrinsic) const override;
/// \brief Returns true if it is beneficial to convert a load of a constant
/// to just the constant itself.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const;
bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
protected:
std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(MVT VT) const;
findRepresentativeClass(MVT VT) const override;
private:
/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
@ -467,7 +465,7 @@ namespace llvm {
/// lower a pair of fmul and fadd to the latter so it's not clear that there
/// would be a gain or that the gain would be worthwhile enough to risk
/// correctness bugs.
virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; }
bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
@ -478,12 +476,12 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals,
bool isThisReturn, SDValue ThisVal) const;
virtual SDValue
SDValue
LowerFormalArguments(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
SDLoc dl, SDValue &Chain,
@ -494,12 +492,12 @@ namespace llvm {
unsigned ArgSize,
bool ForceMutable,
unsigned ByValStoreOffset,
unsigned TotalArgRegsSaveSize) const;
unsigned TotalArgRegsSaveSize) const;
void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
SDLoc dl, SDValue &Chain,
unsigned ArgOffset,
unsigned TotalArgRegsSaveSize,
unsigned TotalArgRegsSaveSize,
bool ForceMutable = false) const;
void computeRegArea(CCState &CCInfo, MachineFunction &MF,
@ -508,12 +506,12 @@ namespace llvm {
unsigned &ArgRegsSize,
unsigned &ArgRegsSaveSize) const;
virtual SDValue
SDValue
LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
/// HandleByVal - Target-specific cleanup for ByVal support.
virtual void HandleByVal(CCState *, unsigned &, unsigned) const;
void HandleByVal(CCState *, unsigned &, unsigned) const override;
/// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Targets which want to do tail call
@ -528,21 +526,21 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const;
virtual bool CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const;
bool CanLowerReturn(CallingConv::ID CallConv,
MachineFunction &MF, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const override;
virtual SDValue
SDValue
LowerReturn(SDValue Chain,
CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const;
SDLoc dl, SelectionDAG &DAG) const override;
virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
bool mayBeEmittedAsTailCall(CallInst *CI) const override;
SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;

6
llvm/lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -97,7 +97,7 @@ namespace {
static char ID;
ARMCGBR() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF) {
bool runOnMachineFunction(MachineFunction &MF) override {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
if (AFI->getGlobalBaseReg() == 0)
return false;
@ -146,11 +146,11 @@ namespace {
return true;
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM PIC Global Base Reg Initialization";
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}

6
llvm/lib/Target/ARM/ARMInstrInfo.h
View File

@ -28,17 +28,17 @@ public:
explicit ARMInstrInfo(const ARMSubtarget &STI);
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void getNoopForMachoTarget(MCInst &NopInst) const;
void getNoopForMachoTarget(MCInst &NopInst) const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
unsigned getUnindexedOpcode(unsigned Opc) const;
unsigned getUnindexedOpcode(unsigned Opc) const override;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
const ARMRegisterInfo &getRegisterInfo() const { return RI; }
const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
};
}

24
llvm/lib/Target/ARM/ARMJITInfo.h
View File

@ -53,45 +53,45 @@ namespace llvm {
/// overwriting OLD with a branch to NEW. This is used for self-modifying
/// code.
///
virtual void replaceMachineCodeForFunction(void *Old, void *New);
void replaceMachineCodeForFunction(void *Old, void *New) override;
/// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter object
/// to emit an indirect symbol which contains the address of the specified
/// ptr.
virtual void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
JITCodeEmitter &JCE);
void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
JITCodeEmitter &JCE) override;
// getStubLayout - Returns the size and alignment of the largest call stub
// on ARM.
virtual StubLayout getStubLayout();
StubLayout getStubLayout() override;
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
/// small native function that simply calls the function at the specified
/// address.
virtual void *emitFunctionStub(const Function* F, void *Fn,
JITCodeEmitter &JCE);
void *emitFunctionStub(const Function* F, void *Fn,
JITCodeEmitter &JCE) override;
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
/// relocate - Before the JIT can run a block of code that has been emitted,
/// it must rewrite the code to contain the actual addresses of any
/// referenced global symbols.
virtual void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char* GOTBase);
void relocate(void *Function, MachineRelocation *MR,
unsigned NumRelocs, unsigned char* GOTBase) override;
/// hasCustomConstantPool - Allows a target to specify that constant
/// pool address resolution is handled by the target.
virtual bool hasCustomConstantPool() const { return true; }
bool hasCustomConstantPool() const override { return true; }
/// hasCustomJumpTables - Allows a target to specify that jumptables
/// are emitted by the target.
virtual bool hasCustomJumpTables() const { return true; }
bool hasCustomJumpTables() const override { return true; }
/// allocateSeparateGVMemory - If true, globals should be placed in
/// separately allocated heap memory rather than in the same
/// code memory allocated by JITCodeEmitter.
virtual bool allocateSeparateGVMemory() const {
bool allocateSeparateGVMemory() const override {
#ifdef __APPLE__
return true;
#else

8
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -69,9 +69,9 @@ namespace {
RegScavenger *RS;
bool isThumb2;
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM load / store optimization pass";
}
@ -1550,9 +1550,9 @@ namespace {
MachineRegisterInfo *MRI;
MachineFunction *MF;
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM pre- register allocation load / store optimization pass";
}

6
llvm/lib/Target/ARM/ARMSelectionDAGInfo.h
View File

@ -44,23 +44,21 @@ public:
explicit ARMSelectionDAGInfo(const TargetMachine &TM);
~ARMSelectionDAGInfo();
virtual
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
SDValue Chain,
SDValue Dst, SDValue Src,
SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const;
MachinePointerInfo SrcPtrInfo) const override;
// Adjust parameters for memset, see RTABI section 4.3.4
virtual
SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
SDValue Chain,
SDValue Op1, SDValue Op2,
SDValue Op3, unsigned Align,
bool isVolatile,
MachinePointerInfo DstPtrInfo) const;
MachinePointerInfo DstPtrInfo) const override;
};
}

4
llvm/lib/Target/ARM/ARMSubtarget.h
View File

@ -240,7 +240,7 @@ protected:
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
/// \brief Reset the features for the ARM target.
virtual void resetSubtargetFeatures(const MachineFunction *MF);
void resetSubtargetFeatures(const MachineFunction *MF) override;
private:
void initializeEnvironment();
void resetSubtargetFeatures(StringRef CPU, StringRef FS);
@ -384,7 +384,7 @@ public:
/// enablePostRAScheduler - True at 'More' optimization.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const;
RegClassVector& CriticalPathRCs) const override;
/// getInstrItins - Return the instruction itineraies based on subtarget
/// selection.

10
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -166,11 +166,11 @@ public:
return *getARMTargetMachine().getSubtargetImpl();
}
virtual bool addPreISel();
virtual bool addInstSelector();
virtual bool addPreRegAlloc();
virtual bool addPreSched2();
virtual bool addPreEmitPass();
bool addPreISel() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPreSched2() override;
bool addPreEmitPass() override;
};
} // namespace

38
llvm/lib/Target/ARM/ARMTargetMachine.h
View File

@ -44,23 +44,23 @@ public:
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
virtual const ARMTargetLowering *getTargetLowering() const {
ARMJITInfo *getJITInfo() override { return &JITInfo; }
const ARMSubtarget *getSubtargetImpl() const override { return &Subtarget; }
const ARMTargetLowering *getTargetLowering() const override {
// Implemented by derived classes
llvm_unreachable("getTargetLowering not implemented");
}
virtual const InstrItineraryData *getInstrItineraryData() const {
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
}
/// \brief Register ARM analysis passes with a pass manager.
virtual void addAnalysisPasses(PassManagerBase &PM);
void addAnalysisPasses(PassManagerBase &PM) override;
// Pass Pipeline Configuration
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE) override;
};
/// ARMTargetMachine - ARM target machine.
@ -79,22 +79,22 @@ class ARMTargetMachine : public ARMBaseTargetMachine {
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL);
virtual const ARMRegisterInfo *getRegisterInfo() const {
const ARMRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
virtual const ARMTargetLowering *getTargetLowering() const {
const ARMTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
virtual const ARMFrameLowering *getFrameLowering() const {
const ARMFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const DataLayout *getDataLayout() const { return &DL; }
const ARMInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const DataLayout *getDataLayout() const override { return &DL; }
};
/// ThumbTargetMachine - Thumb target machine.
@ -118,27 +118,27 @@ public:
CodeGenOpt::Level OL);
/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
const ARMBaseRegisterInfo *getRegisterInfo() const override {
return &InstrInfo->getRegisterInfo();
}
virtual const ARMTargetLowering *getTargetLowering() const {
const ARMTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
const ARMSelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
/// returns either Thumb1InstrInfo or Thumb2InstrInfo
virtual const ARMBaseInstrInfo *getInstrInfo() const {
const ARMBaseInstrInfo *getInstrInfo() const override {
return InstrInfo.get();
}
/// returns either Thumb1FrameLowering or ARMFrameLowering
virtual const ARMFrameLowering *getFrameLowering() const {
const ARMFrameLowering *getFrameLowering() const override {
return FrameLowering.get();
}
virtual const DataLayout *getDataLayout() const { return &DL; }
const DataLayout *getDataLayout() const override { return &DL; }
};
} // end namespace llvm

37
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
View File

@ -52,7 +52,7 @@ public:
initializeARMTTIPass(*PassRegistry::getPassRegistry());
}
virtual void initializePass() override {
void initializePass() override {
pushTTIStack(this);
}
@ -60,7 +60,7 @@ public:
popTTIStack();
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const override {
void getAnalysisUsage(AnalysisUsage &AU) const override {
TargetTransformInfo::getAnalysisUsage(AU);
}
@ -68,7 +68,7 @@ public:
static char ID;
/// Provide necessary pointer adjustments for the two base classes.
virtual void *getAdjustedAnalysisPointer(const void *ID) override {
void *getAdjustedAnalysisPointer(const void *ID) override {
if (ID == &TargetTransformInfo::ID)
return (TargetTransformInfo*)this;
return this;
@ -77,8 +77,7 @@ public:
/// \name Scalar TTI Implementations
/// @{
using TargetTransformInfo::getIntImmCost;
virtual unsigned
getIntImmCost(const APInt &Imm, Type *Ty) const override;
unsigned getIntImmCost(const APInt &Imm, Type *Ty) const override;
/// @}
@ -86,7 +85,7 @@ public:
/// \name Vector TTI Implementations
/// @{
unsigned getNumberOfRegisters(bool Vector) const {
unsigned getNumberOfRegisters(bool Vector) const override {
if (Vector) {
if (ST->hasNEON())
return 16;
@ -98,7 +97,7 @@ public:
return 13;
}
unsigned getRegisterBitWidth(bool Vector) const {
unsigned getRegisterBitWidth(bool Vector) const override {
if (Vector) {
if (ST->hasNEON())
return 128;
@ -108,7 +107,7 @@ public:
return 32;
}
unsigned getMaximumUnrollFactor() const {
unsigned getMaximumUnrollFactor() const override {
// These are out of order CPUs:
if (ST->isCortexA15() || ST->isSwift())
return 2;
@ -116,23 +115,27 @@ public:
}
unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
int Index, Type *SubTp) const;
int Index, Type *SubTp) const override;
unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
Type *Src) const;
Type *Src) const override;
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) const;
unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
Type *CondTy) const override;
unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) const;
unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
unsigned Index) const override;
unsigned getAddressComputationCost(Type *Val, bool IsComplex) const;
unsigned getAddressComputationCost(Type *Val,
bool IsComplex) const override;
unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
OperandValueKind Op1Info = OK_AnyValue,
OperandValueKind Op2Info = OK_AnyValue) const;
unsigned
getArithmeticInstrCost(unsigned Opcode, Type *Ty,
OperandValueKind Op1Info = OK_AnyValue,
OperandValueKind Op2Info = OK_AnyValue) const override;
unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
unsigned AddressSpace) const;
unsigned AddressSpace) const override;
/// @}
};

4
llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
View File

@ -26,8 +26,8 @@ public:
ARMInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

10
llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h
View File

@ -56,16 +56,16 @@ public:
/// @}
void PrintImpl(raw_ostream &OS) const;
void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const;
void AddValueSymbols(MCAssembler *) const;
const MCSection *FindAssociatedSection() const {
const MCAsmLayout *Layout) const override;
void AddValueSymbols(MCAssembler *) const override;
const MCSection *FindAssociatedSection() const override {
return getSubExpr()->FindAssociatedSection();
}
// There are no TLS ARMMCExprs at the moment.
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;

4
llvm/lib/Target/ARM/MLxExpansionPass.cpp
View File

@ -40,9 +40,9 @@ namespace {
static char ID;
MLxExpansion() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "ARM MLA / MLS expansion pass";
}

21
llvm/lib/Target/ARM/Thumb1FrameLowering.h
View File

@ -32,23 +32,24 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function.
void emitPrologue(MachineFunction &MF) const;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const override;
bool hasReservedCallFrame(const MachineFunction &MF) const;
bool hasReservedCallFrame(const MachineFunction &MF) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
void
eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const override;
};
} // End llvm namespace

12
llvm/lib/Target/ARM/Thumb1InstrInfo.h
View File

@ -27,33 +27,33 @@ public:
explicit Thumb1InstrInfo(const ARMSubtarget &STI);
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void getNoopForMachoTarget(MCInst &NopInst) const;
void getNoopForMachoTarget(MCInst &NopInst) const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
unsigned getUnindexedOpcode(unsigned Opc) const;
unsigned getUnindexedOpcode(unsigned Opc) const override;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
const Thumb1RegisterInfo &getRegisterInfo() const { return RI; }
const Thumb1RegisterInfo &getRegisterInfo() const override { return RI; }
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool KillSrc) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
};
}

27
llvm/lib/Target/ARM/Thumb1RegisterInfo.h
View File

@ -27,21 +27,20 @@ struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
public:
Thumb1RegisterInfo(const ARMSubtarget &STI);
const TargetRegisterClass*
getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
const TargetRegisterClass *
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
const TargetRegisterClass*
getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
const TargetRegisterClass *
getPointerRegClass(const MachineFunction &MF,
unsigned Kind = 0) const override;
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
DebugLoc dl,
unsigned DestReg, unsigned SubIdx, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0,
unsigned MIFlags = MachineInstr::NoFlags) const;
void
emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
unsigned MIFlags = MachineInstr::NoFlags) const override;
// rewrite MI to access 'Offset' bytes from the FP. Update Offset to be
// however much remains to be handled. Return 'true' if no further
@ -50,15 +49,15 @@ public:
unsigned FrameReg, int &Offset,
const ARMBaseInstrInfo &TII) const;
void resolveFrameIndex(MachineBasicBlock::iterator I,
unsigned BaseReg, int64_t Offset) const;
unsigned BaseReg, int64_t Offset) const override;
bool saveScavengerRegister(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
MachineBasicBlock::iterator &UseMI,
const TargetRegisterClass *RC,
unsigned Reg) const;
unsigned Reg) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = NULL) const;
RegScavenger *RS = NULL) const override;
};
}

4
llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
View File

@ -33,9 +33,9 @@ namespace {
const TargetRegisterInfo *TRI;
ARMFunctionInfo *AFI;
virtual bool runOnMachineFunction(MachineFunction &Fn);
bool runOnMachineFunction(MachineFunction &Fn) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Thumb IT blocks insertion pass";
}

16
llvm/lib/Target/ARM/Thumb2InstrInfo.h
View File

@ -28,40 +28,40 @@ public:
explicit Thumb2InstrInfo(const ARMSubtarget &STI);
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void getNoopForMachoTarget(MCInst &NopInst) const;
void getNoopForMachoTarget(MCInst &NopInst) const override;
// Return the non-pre/post incrementing version of 'Opc'. Return 0
// if there is not such an opcode.
unsigned getUnindexedOpcode(unsigned Opc) const;
unsigned getUnindexedOpcode(unsigned Opc) const override;
void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
MachineBasicBlock *NewDest) const;
MachineBasicBlock *NewDest) const override;
bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) const;
MachineBasicBlock::iterator MBBI) const override;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
bool KillSrc) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const;
const TargetRegisterInfo *TRI) const override;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
const Thumb2RegisterInfo &getRegisterInfo() const override { return RI; }
};
/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical

12
llvm/lib/Target/ARM/Thumb2RegisterInfo.h
View File

@ -29,13 +29,11 @@ public:
/// emitLoadConstPool - Emits a load from constpool to materialize the
/// specified immediate.
void emitLoadConstPool(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &MBBI,
DebugLoc dl,
unsigned DestReg, unsigned SubIdx, int Val,
ARMCC::CondCodes Pred = ARMCC::AL,
unsigned PredReg = 0,
unsigned MIFlags = MachineInstr::NoFlags) const;
void
emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
unsigned MIFlags = MachineInstr::NoFlags) const override;
};
}

4
llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
View File

@ -137,9 +137,9 @@ namespace {
const Thumb2InstrInfo *TII;
const ARMSubtarget *STI;
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Thumb2 instruction size reduction pass";
}