forked from OSchip/llvm-project
[VE] Add setcc for fp128
Add setcc for fp128 and clean existing ISel patterns. Also add a regression test. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89683
This commit is contained in:
Kazushi (Jam) Marukawa
parent
fb2bb6fad4
commit
6bb60d3e26
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@ -1788,47 +1788,27 @@ def GETSTACKTOP : Pseudo<(outs I64:$dst), (ins),
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// or %res, 0, (0)1 ; initialize by 0
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// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
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def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)),
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(EXTRACT_SUBREG
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(CMOVLrm (icond2cc $cond),
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(CMPSLrr i64:$LHS, i64:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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class setccrr<Instruction INSN> :
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OutPatFrag<(ops node:$cond, node:$comp),
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(EXTRACT_SUBREG
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(INSN $cond, $comp,
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!add(63, 64), // means (63)0 == 1
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)),
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(EXTRACT_SUBREG
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(CMOVLrm (icond2cc $cond),
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(CMPULrr i64:$LHS, i64:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)),
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(EXTRACT_SUBREG
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(CMOVWrm (icond2cc $cond),
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(CMPSWSXrr i32:$LHS, i32:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCUIOp:$cond)),
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(EXTRACT_SUBREG
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(CMOVWrm (icond2cc $cond),
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(CMPUWrr i32:$LHS, i32:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc f64:$LHS, f64:$RHS, cond:$cond)),
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(EXTRACT_SUBREG
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(CMOVDrm (fcond2cc $cond),
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(FCMPDrr f64:$LHS, f64:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)),
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(EXTRACT_SUBREG
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(CMOVSrm (fcond2cc $cond),
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(FCMPSrr f32:$LHS, f32:$RHS),
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!add(63, 64),
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(ORim 0, 0)), sub_i32)>;
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def : Pat<(i32 (setcc i32:$l, i32:$r, CCSIOp:$cond)),
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(setccrr<CMOVWrm> (icond2cc $cond), (CMPSWSXrr $l, $r))>;
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def : Pat<(i32 (setcc i32:$l, i32:$r, CCUIOp:$cond)),
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(setccrr<CMOVWrm> (icond2cc $cond), (CMPUWrr $l, $r))>;
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def : Pat<(i32 (setcc i64:$l, i64:$r, CCSIOp:$cond)),
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(setccrr<CMOVLrm> (icond2cc $cond), (CMPSLrr $l, $r))>;
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def : Pat<(i32 (setcc i64:$l, i64:$r, CCUIOp:$cond)),
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(setccrr<CMOVLrm> (icond2cc $cond), (CMPULrr $l, $r))>;
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def : Pat<(i32 (setcc f32:$l, f32:$r, cond:$cond)),
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(setccrr<CMOVSrm> (fcond2cc $cond), (FCMPSrr $l, $r))>;
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def : Pat<(i32 (setcc f64:$l, f64:$r, cond:$cond)),
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(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPDrr $l, $r))>;
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def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
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(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;
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// Special SELECTCC pattern matches
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// Use min/max for better performance.
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@ -0,0 +1,193 @@
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; RUN: llc < %s -mtriple=ve | FileCheck %s
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;;; Test all combination of input type and output type among following types.
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;;;
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;;; Types:
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;;; i1/i8/u8/i16/u16/i32/u32/i64/u64/i128/u128/float/double/fp128
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i1(i1 zeroext %0, i1 zeroext %1) {
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; CHECK-LABEL: setcc_i1:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s0, %s0, %s1
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; CHECK-NEXT: xor %s0, 1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = xor i1 %0, %1
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%4 = xor i1 %3, true
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ret i1 %4
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i8(i8 signext %0, i8 signext %1) {
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; CHECK-LABEL: setcc_i8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i8 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_u8(i8 zeroext %0, i8 zeroext %1) {
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; CHECK-LABEL: setcc_u8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i8 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i16(i16 signext %0, i16 signext %1) {
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; CHECK-LABEL: setcc_i16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i16 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_u16(i16 zeroext %0, i16 zeroext %1) {
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; CHECK-LABEL: setcc_u16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i16 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i32(i32 signext %0, i32 signext %1) {
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; CHECK-LABEL: setcc_i32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i32 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_u32(i32 zeroext %0, i32 zeroext %1) {
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; CHECK-LABEL: setcc_u32:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.w.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i32 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i64(i64 %0, i64 %1) {
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; CHECK-LABEL: setcc_i64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.l %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i64 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_u64(i64 %0, i64 %1) {
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; CHECK-LABEL: setcc_u64:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: cmps.l %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i64 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_i128(i128 %0, i128 %1) {
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; CHECK-LABEL: setcc_i128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s1, %s1, %s3
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; CHECK-NEXT: xor %s0, %s0, %s2
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmps.l %s0, %s0, %s1
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; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i128 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_u128(i128 %0, i128 %1) {
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; CHECK-LABEL: setcc_u128:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: xor %s1, %s1, %s3
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; CHECK-NEXT: xor %s0, %s0, %s2
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; CHECK-NEXT: or %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmps.l %s0, %s0, %s1
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; CHECK-NEXT: cmov.l.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = icmp eq i128 %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_float(float %0, float %1) {
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; CHECK-LABEL: setcc_float:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: fcmp.s %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.s.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = fcmp fast oeq float %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_double(double %0, double %1) {
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; CHECK-LABEL: setcc_double:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: fcmp.d %s0, %s0, %s1
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = fcmp fast oeq double %0, %1
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ret i1 %3
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}
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; Function Attrs: norecurse nounwind readnone
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define zeroext i1 @setcc_quad(fp128 %0, fp128 %1) {
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; CHECK-LABEL: setcc_quad:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: fcmp.q %s0, %s0, %s2
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; CHECK-NEXT: or %s1, 0, (0)1
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; CHECK-NEXT: cmov.d.eq %s1, (63)0, %s0
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; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
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; CHECK-NEXT: or %s11, 0, %s9
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%3 = fcmp fast oeq fp128 %0, %1
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ret i1 %3
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}
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