forked from OSchip/llvm-project
[LoopVectorize] Add support for invariant stores of ordered reductions
Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D126772
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@ -1017,11 +1017,10 @@ bool LoopVectorizationLegality::canVectorizeFPMath(
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// We can now only vectorize if all reductions with Exact FP math also
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// have the isOrdered flag set, which indicates that we can move the
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// reduction operations in-loop, and do not have intermediate store.
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// reduction operations in-loop.
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return (all_of(getReductionVars(), [&](auto &Reduction) -> bool {
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const RecurrenceDescriptor &RdxDesc = Reduction.second;
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return !RdxDesc.hasExactFPMath() ||
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(RdxDesc.isOrdered() && !RdxDesc.IntermediateStore);
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return !RdxDesc.hasExactFPMath() || RdxDesc.isOrdered();
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}));
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}
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@ -1361,10 +1361,34 @@ declare float @llvm.fmuladd.f32(float, float, float)
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; Test case with invariant store where fadd is strict.
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define void @reduction_store_to_invariant_address(float* %dst, float* readonly %src) {
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; CHECK-ORDERED-LABEL: @reduction_store_to_invariant_address(
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; CHECK-ORDERED-NOT: vector.body
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; CHECK-ORDERED: entry
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; CHECK-ORDERED: %[[DEST_PTR:.*]] = getelementptr inbounds float, float* %dst, i64 42
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; CHECK-ORDERED: vector.body
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; CHECK-ORDERED: %[[VEC_PHI:.*]] = phi float [ 0.000000e+00, %vector.ph ], [ %[[RDX:.*]], %vector.body ]
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; CHECK-ORDERED: %[[LOAD_VEC:.*]] = load <8 x float>, <8 x float>*
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; CHECK-ORDERED: %[[RDX:.*]] = call float @llvm.vector.reduce.fadd.v8f32(float %[[VEC_PHI]], <8 x float> %[[LOAD_VEC]])
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; CHECK-ORDERED: middle.block
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; CHECK-ORDERED: store float %[[RDX]], float* %[[DEST_PTR]]
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; CHECK-ORDERED: for.body
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; CHECK-ORDERED: %[[LOAD:.*]] = load float, float*
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; CHECK-ORDERED: %[[FADD:.*]] = fadd float %{{.*}}, %[[LOAD]]
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; CHECK-ORDERED: store float %[[FADD]], float* %[[DEST_PTR]]
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; CHECK-UNORDERED-LABEL: @reduction_store_to_invariant_address(
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; CHECK-UNORDERED-NOT: vector.body
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; CHECK-UNORDERED: entry
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; CHECK-UNORDERED: %[[DEST_PTR:.*]] = getelementptr inbounds float, float* %dst, i64 42
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; CHECK-UNORDERED: vector.body
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; CHECK-UNORDERED: %[[VEC_PHI:.*]] = phi <8 x float> [ <float 0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %vector.ph ], [ %[[FADD_VEC:.*]], %vector.body ]
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; CHECK-UNORDERED: %[[LOAD_VEC:.*]] = load <8 x float>, <8 x float>*
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; CHECK-UNORDERED: %[[FADD_VEC]] = fadd <8 x float> %[[VEC_PHI]], %[[LOAD_VEC]]
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; CHECK-UNORDERED-NOT: call float @llvm.vector.reduce.fadd
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; CHECK-UNORDERED: middle.block
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; CHECK-UNORDERED: %[[RDX:.*]] = call float @llvm.vector.reduce.fadd.v8f32(float -0.000000e+00, <8 x float> %[[FADD_VEC]])
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; CHECK-UNORDERED: store float %[[RDX]], float* %[[DEST_PTR]]
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; CHECK-UNORDERED: for.body
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; CHECK-UNORDERED: %[[LOAD:.*]] = load float, float*
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; CHECK-UNORDERED: %[[FADD:.*]] = fadd float {{.*}}, %[[LOAD]]
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; CHECK-UNORDERED: store float %[[FADD]], float* %[[DEST_PTR]]
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; CHECK-NOT-VECTORIZED-LABEL: @reduction_store_to_invariant_address(
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; CHECK-NOT-VECTORIZED-NOT: vector.body
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@ -1383,7 +1407,7 @@ for.body:
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store float %add, float* %arrayidx, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1000
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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br i1 %exitcond, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup:
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ret void
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