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[AArch64] Adjust the cost model for Exynos M3 

Fix typo and simplify matching expression.

llvm-svn: 329130
This commit is contained in:
Evandro Menezes 2018-04-03 22:57:17 +00:00
parent 1376d934ed
commit 6b8d8f4010
1 changed files with 12 additions and 12 deletions
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24
llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
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@ -109,15 +109,15 @@ def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
//===----------------------------------------------------------------------===//
// Predicates.
def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
MI->getOperand(0).isReg() &&
MI->getOperand(0).getReg() != AArch64::LR}]>;
def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
def M3RotateFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
MI->getOpcode() == AArch64::EXTRXrri) &&
MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
MI->getOperand(0).isReg() &&
MI->getOperand(0).getReg() != AArch64::LR}]>;
def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
MI->getOpcode() == AArch64::EXTRXrri) &&
MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
//===----------------------------------------------------------------------===//
// Coarse scheduling model.
@ -143,8 +143,8 @@ def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>,
SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
SchedVar<NoSchedPred, [M3WriteAA]>]>;
def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateFastPred, [M3WriteA1]>,
SchedVar<NoSchedPred, [M3WriteAA]>]>;
def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>,
SchedVar<NoSchedPred, [M3WriteAA]>]>;
def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
@ -509,7 +509,7 @@ def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>;
// Divide and multiply instructions.
// Miscellaneous instructions.
def : InstRW<[M3WriteAY], (instregex "^EXTR[WX]rri")>;
def : InstRW<[M3WriteAY], (instrs EXTRWrri, EXTRXrri)>;
// Load instructions.
def : InstRW<[M3WriteLD,