forked from OSchip/llvm-project
[X86] Fix incomplete handling of register-assigned variables in parsing.
Teach x86 assembly operand parsing to distinguish between assembler variable assigned to named registers and those assigned to immediate values. Reviewers: rnk, nickdesaulniers, void Subscribers: hiraditya, jyknight, llvm-commits Differential Revision: https://reviews.llvm.org/D56287 llvm-svn: 350966
This commit is contained in:
Nirav Dave
parent
d0de9890d3
commit
6b7f5aac72
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@ -804,8 +804,8 @@ private:
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return Parser.Error(L, Msg, Range);
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}
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std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
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Error(Loc, Msg);
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std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg, SMRange R = SMRange()) {
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Error(Loc, Msg, R);
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return nullptr;
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}
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@ -835,7 +835,10 @@ private:
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InlineAsmIdentifierInfo &Info,
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bool IsUnevaluatedOperand, SMLoc &End);
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std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc MemStart);
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std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
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const MCExpr *&Disp,
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const SMLoc &StartLoc,
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SMLoc &EndLoc);
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bool ParseIntelMemoryOperandSize(unsigned &Size);
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std::unique_ptr<X86Operand>
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@ -1102,10 +1105,13 @@ bool X86AsmParser::ParseRegister(unsigned &RegNo,
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if (RegNo == X86::RIZ || RegNo == X86::RIP ||
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X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
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X86II::isX86_64NonExtLowByteReg(RegNo) ||
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X86II::isX86_64ExtendedReg(RegNo))
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return Error(StartLoc, "register %"
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+ Tok.getString() + " is only available in 64-bit mode",
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X86II::isX86_64ExtendedReg(RegNo)) {
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StringRef RegName = Tok.getString();
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Parser.Lex(); // Eat register name.
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return Error(StartLoc,
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"register %" + RegName + " is only available in 64-bit mode",
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SMRange(StartLoc, EndLoc));
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}
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}
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// Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
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@ -1935,49 +1941,61 @@ std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
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std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
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MCAsmParser &Parser = getParser();
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switch (getLexer().getKind()) {
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default:
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// Parse a memory operand with no segment register.
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return ParseMemOperand(0, Parser.getTok().getLoc());
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case AsmToken::Percent: {
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// Read the register.
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unsigned RegNo;
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SMLoc Start, End;
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if (ParseRegister(RegNo, Start, End)) return nullptr;
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if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
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Error(Start, "%eiz and %riz can only be used as index registers",
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SMRange(Start, End));
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return nullptr;
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}
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if (RegNo == X86::RIP) {
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Error(Start, "%rip can only be used as a base register",
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SMRange(Start, End));
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return nullptr;
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}
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// If this is a segment register followed by a ':', then this is the start
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// of a memory reference, otherwise this is a normal register reference.
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if (getLexer().isNot(AsmToken::Colon))
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return X86Operand::CreateReg(RegNo, Start, End);
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if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
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return ErrorOperand(Start, "invalid segment register");
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getParser().Lex(); // Eat the colon.
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return ParseMemOperand(RegNo, Start);
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}
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case AsmToken::Dollar: {
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// $42 -> immediate.
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// $42 or $ID -> immediate.
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SMLoc Start = Parser.getTok().getLoc(), End;
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Parser.Lex();
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const MCExpr *Val;
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if (getParser().parseExpression(Val, End))
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// This is an immediate, so we should not parse a register. Do a precheck
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// for '%' to supercede intra-register parse errors.
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SMLoc L = Parser.getTok().getLoc();
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if (check(getLexer().is(AsmToken::Percent), L,
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"expected immediate expression") ||
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getParser().parseExpression(Val, End) ||
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check(isa<X86MCExpr>(Val), L, "expected immediate expression"))
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return nullptr;
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return X86Operand::CreateImm(Val, Start, End);
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}
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case AsmToken::LCurly:{
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case AsmToken::LCurly: {
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SMLoc Start = Parser.getTok().getLoc();
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return ParseRoundingModeOp(Start);
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}
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default: {
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// This a memory operand or a register. We have some parsing complications
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// as a '(' may be part of an immediate expression or the addressing mode
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// block. This is complicated by the fact that an assembler-level variable
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// may refer either to a register or an immediate expression.
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SMLoc Loc = Parser.getTok().getLoc(), EndLoc;
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const MCExpr *Expr = nullptr;
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unsigned Reg = 0;
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if (getLexer().isNot(AsmToken::LParen)) {
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// No '(' so this is either a displacement expression or a register.
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if (Parser.parseExpression(Expr, EndLoc))
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return nullptr;
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if (auto *RE = dyn_cast<X86MCExpr>(Expr)) {
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// Segment Register. Reset Expr and copy value to register.
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Expr = nullptr;
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Reg = RE->getRegNo();
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// Sanity check register.
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if (Reg == X86::EIZ || Reg == X86::RIZ)
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return ErrorOperand(
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Loc, "%eiz and %riz can only be used as index registers",
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SMRange(Loc, EndLoc));
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if (Reg == X86::RIP)
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return ErrorOperand(Loc, "%rip can only be used as a base register",
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SMRange(Loc, EndLoc));
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// Return register that are not segment prefixes immediately.
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if (!Parser.parseOptionalToken(AsmToken::Colon))
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return X86Operand::CreateReg(Reg, Loc, EndLoc);
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if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(Reg))
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return ErrorOperand(Loc, "invalid segment register");
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}
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}
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// This is a Memory operand.
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return ParseMemOperand(Reg, Expr, Loc, EndLoc);
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}
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}
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}
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@ -2086,199 +2104,201 @@ bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
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return false;
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}
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
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/// has already been parsed if present.
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/// ParseMemOperand: 'seg : disp(basereg, indexreg, scale)'. The '%ds:' prefix
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/// has already been parsed if present. disp may be provided as well.
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std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
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SMLoc MemStart) {
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const MCExpr *&Disp,
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const SMLoc &StartLoc,
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SMLoc &EndLoc) {
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MCAsmParser &Parser = getParser();
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
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// only way to do this without lookahead is to eat the '(' and see what is
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// after it.
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const MCExpr *Disp = MCConstantExpr::create(0, getParser().getContext());
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if (getLexer().isNot(AsmToken::LParen)) {
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SMLoc ExprEnd;
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if (getParser().parseExpression(Disp, ExprEnd)) return nullptr;
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// Disp may be a variable, handle register values.
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if (auto *RE = dyn_cast<X86MCExpr>(Disp))
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return X86Operand::CreateReg(RE->getRegNo(), MemStart, ExprEnd);
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SMLoc Loc;
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// Based on the initial passed values, we may be in any of these cases, we are
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// in one of these cases (with current position (*)):
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, ExprEnd);
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return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
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MemStart, ExprEnd);
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// 1. seg : * disp (base-index-scale-expr)
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// 2. seg : *(disp) (base-index-scale-expr)
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// 3. seg : *(base-index-scale-expr)
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// 4. disp *(base-index-scale-expr)
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// 5. *(disp) (base-index-scale-expr)
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// 6. *(base-index-scale-expr)
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// 7. disp *
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// 8. *(disp)
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// If we do not have an displacement yet, check if we're in cases 4 or 6 by
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// checking if the first object after the parenthesis is a register (or an
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// identifier referring to a register) and parse the displacement or default
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// to 0 as appropriate.
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auto isAtMemOperand = [this]() {
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if (this->getLexer().isNot(AsmToken::LParen))
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return false;
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AsmToken Buf[2];
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StringRef Id;
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auto TokCount = this->getLexer().peekTokens(Buf, true);
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if (TokCount == 0)
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return false;
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switch (Buf[0].getKind()) {
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case AsmToken::Percent:
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case AsmToken::Comma:
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return true;
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// These lower cases are doing a peekIdentifier.
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case AsmToken::At:
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case AsmToken::Dollar:
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if ((TokCount > 1) &&
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(Buf[1].is(AsmToken::Identifier) || Buf[1].is(AsmToken::String)) &&
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(Buf[0].getLoc().getPointer() + 1 == Buf[1].getLoc().getPointer()))
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Id = StringRef(Buf[0].getLoc().getPointer(),
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Buf[1].getIdentifier().size() + 1);
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break;
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case AsmToken::Identifier:
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case AsmToken::String:
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Id = Buf[0].getIdentifier();
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break;
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default:
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return false;
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}
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// Eat the '('.
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Parser.Lex();
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} else {
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// Okay, we have a '('. We don't know if this is an expression or not, but
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// so we have to eat the ( to see beyond it.
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SMLoc LParenLoc = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the '('.
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if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
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// Nothing to do here, fall into the code below with the '(' part of the
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// memory operand consumed.
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} else {
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SMLoc ExprEnd;
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getLexer().UnLex(AsmToken(AsmToken::LParen, "("));
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// It must be either an parenthesized expression, or an expression that
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// begins from a parenthesized expression, parse it now. Example: (1+2) or
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// (1+2)+3
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if (getParser().parseExpression(Disp, ExprEnd))
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return nullptr;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(getPointerWidth(), Disp, LParenLoc,
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ExprEnd);
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return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
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MemStart, ExprEnd);
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// We have an ID. Check if it is bound to a register.
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if (!Id.empty()) {
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MCSymbol *Sym = this->getContext().getOrCreateSymbol(Id);
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if (Sym->isVariable()) {
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auto V = Sym->getVariableValue(/*SetUsed*/ false);
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return isa<X86MCExpr>(V);
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}
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}
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return false;
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};
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// Eat the '('.
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Parser.Lex();
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if (!Disp) {
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// Parse immediate if we're not at a mem operand yet.
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if (!isAtMemOperand()) {
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if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(Disp, EndLoc))
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return nullptr;
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assert(!isa<X86MCExpr>(Disp) && "Expected non-register here.");
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} else {
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// Disp is implicitly zero if we haven't parsed it yet.
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Disp = MCConstantExpr::create(0, Parser.getContext());
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}
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}
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// If we reached here, then we just ate the ( of the memory operand. Process
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// We are now either at the end of the operand or at the '(' at the start of a
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// base-index-scale-expr.
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if (!parseOptionalToken(AsmToken::LParen)) {
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if (SegReg == 0)
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return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
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return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
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StartLoc, EndLoc);
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}
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// If we reached here, then eat the '(' and Process
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// the rest of the memory operand.
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unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
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SMLoc IndexLoc, BaseLoc;
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SMLoc BaseLoc = getLexer().getLoc();
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const MCExpr *E;
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StringRef ErrMsg;
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if (getLexer().is(AsmToken::Percent)) {
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SMLoc StartLoc, EndLoc;
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BaseLoc = Parser.getTok().getLoc();
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if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;
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if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
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Error(StartLoc, "eiz and riz can only be used as index registers",
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SMRange(StartLoc, EndLoc));
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// Parse BaseReg if one is provided.
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if (getLexer().isNot(AsmToken::Comma) && getLexer().isNot(AsmToken::RParen)) {
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if (Parser.parseExpression(E, EndLoc) ||
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check(!isa<X86MCExpr>(E), BaseLoc, "expected register here"))
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return nullptr;
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}
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// Sanity check register.
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BaseReg = cast<X86MCExpr>(E)->getRegNo();
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if (BaseReg == X86::EIZ || BaseReg == X86::RIZ)
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return ErrorOperand(BaseLoc,
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"eiz and riz can only be used as index registers",
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SMRange(BaseLoc, EndLoc));
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}
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if (getLexer().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat the comma.
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IndexLoc = Parser.getTok().getLoc();
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if (parseOptionalToken(AsmToken::Comma)) {
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// Following the comma we should have either an index register, or a scale
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// value. We don't support the later form, but we want to parse it
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// correctly.
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//
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// Not that even though it would be completely consistent to support syntax
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// like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
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if (getLexer().is(AsmToken::Percent)) {
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SMLoc L;
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if (ParseRegister(IndexReg, L, L))
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// Even though it would be completely consistent to support syntax like
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// "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
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if (getLexer().isNot(AsmToken::RParen)) {
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if (Parser.parseTokenLoc(Loc) || Parser.parseExpression(E, EndLoc))
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return nullptr;
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if (BaseReg == X86::RIP) {
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Error(IndexLoc, "%rip as base register can not have an index register");
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return nullptr;
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}
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if (IndexReg == X86::RIP) {
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Error(IndexLoc, "%rip is not allowed as an index register");
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return nullptr;
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}
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if (getLexer().isNot(AsmToken::RParen)) {
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// Parse the scale amount:
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// ::= ',' [scale-expression]
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if (parseToken(AsmToken::Comma, "expected comma in scale expression"))
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return nullptr;
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if (!isa<X86MCExpr>(E)) {
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// We've parsed an unexpected Scale Value instead of an index
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// register. Interpret it as an absolute.
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int64_t ScaleVal;
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if (!E->evaluateAsAbsolute(ScaleVal, getStreamer().getAssemblerPtr()))
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return ErrorOperand(Loc, "expected absolute expression");
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if (ScaleVal != 1)
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Warning(Loc, "scale factor without index register is ignored");
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Scale = 1;
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} else { // IndexReg Found.
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IndexReg = cast<X86MCExpr>(E)->getRegNo();
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if (getLexer().isNot(AsmToken::RParen)) {
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SMLoc Loc = Parser.getTok().getLoc();
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if (BaseReg == X86::RIP)
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return ErrorOperand(
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Loc, "%rip as base register can not have an index register");
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if (IndexReg == X86::RIP)
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return ErrorOperand(Loc, "%rip is not allowed as an index register");
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int64_t ScaleVal;
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if (getParser().parseAbsoluteExpression(ScaleVal)){
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Error(Loc, "expected scale expression");
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return nullptr;
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if (parseOptionalToken(AsmToken::Comma)) {
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// Parse the scale amount:
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// ::= ',' [scale-expression]
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// A scale amount without an index is ignored.
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if (getLexer().isNot(AsmToken::RParen)) {
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int64_t ScaleVal;
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if (Parser.parseTokenLoc(Loc) ||
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Parser.parseAbsoluteExpression(ScaleVal))
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return ErrorOperand(Loc, "expected scale expression");
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Scale = (unsigned)ScaleVal;
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// Validate the scale amount.
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if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
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Scale != 1)
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return ErrorOperand(Loc,
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"scale factor in 16-bit address must be 1");
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if (checkScale(Scale, ErrMsg))
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return ErrorOperand(Loc, ErrMsg);
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}
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// Validate the scale amount.
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if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
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ScaleVal != 1) {
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Error(Loc, "scale factor in 16-bit address must be 1");
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return nullptr;
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}
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if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 &&
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ScaleVal != 8) {
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Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
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return nullptr;
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}
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Scale = (unsigned)ScaleVal;
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}
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}
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} else if (getLexer().isNot(AsmToken::RParen)) {
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// A scale amount without an index is ignored.
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// index.
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SMLoc Loc = Parser.getTok().getLoc();
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int64_t Value;
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if (getParser().parseAbsoluteExpression(Value))
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return nullptr;
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if (Value != 1)
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Warning(Loc, "scale factor without index register is ignored");
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Scale = 1;
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}
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}
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|
||||
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
|
||||
SMLoc MemEnd = Parser.getTok().getEndLoc();
|
||||
if (parseToken(AsmToken::RParen, "unexpected token in memory operand"))
|
||||
return nullptr;
|
||||
|
||||
// This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
|
||||
// "outb %al, %dx". Out doesn't take a memory form, but this is a widely
|
||||
// documented form in various unofficial manuals, so a lot of code uses it.
|
||||
if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 &&
|
||||
SegReg == 0 && isa<MCConstantExpr>(Disp) &&
|
||||
cast<MCConstantExpr>(Disp)->getValue() == 0)
|
||||
// This is to support otherwise illegal operand (%dx) found in various
|
||||
// unofficial manuals examples (e.g. "out[s]?[bwl]? %al, (%dx)") and must now
|
||||
// be supported. Mark such DX variants separately fix only in special cases.
|
||||
if (BaseReg == X86::DX && IndexReg == 0 && Scale == 1 && SegReg == 0 &&
|
||||
isa<MCConstantExpr>(Disp) && cast<MCConstantExpr>(Disp)->getValue() == 0)
|
||||
return X86Operand::CreateDXReg(BaseLoc, BaseLoc);
|
||||
|
||||
StringRef ErrMsg;
|
||||
if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, is64BitMode(),
|
||||
ErrMsg)) {
|
||||
Error(BaseLoc, ErrMsg);
|
||||
return nullptr;
|
||||
}
|
||||
ErrMsg))
|
||||
return ErrorOperand(BaseLoc, ErrMsg);
|
||||
|
||||
if (SegReg || BaseReg || IndexReg)
|
||||
return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
|
||||
IndexReg, Scale, MemStart, MemEnd);
|
||||
return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd);
|
||||
IndexReg, Scale, StartLoc, EndLoc);
|
||||
return X86Operand::CreateMem(getPointerWidth(), Disp, StartLoc, EndLoc);
|
||||
}
|
||||
|
||||
// Parse either a standard primary expression or a register.
|
||||
bool X86AsmParser::parsePrimaryExpr(const MCExpr *&Res, SMLoc &EndLoc) {
|
||||
MCAsmParser &Parser = getParser();
|
||||
if (Parser.parsePrimaryExpr(Res, EndLoc)) {
|
||||
// See if this is a register first.
|
||||
if (getTok().is(AsmToken::Percent) ||
|
||||
(isParsingIntelSyntax() && getTok().is(AsmToken::Identifier) &&
|
||||
MatchRegisterName(Parser.getTok().getString()))) {
|
||||
SMLoc StartLoc = Parser.getTok().getLoc();
|
||||
// Normal Expression parse fails, check if it could be a register.
|
||||
unsigned RegNo;
|
||||
bool TryRegParse =
|
||||
getTok().is(AsmToken::Percent) ||
|
||||
(isParsingIntelSyntax() && getTok().is(AsmToken::Identifier));
|
||||
if (!TryRegParse || ParseRegister(RegNo, StartLoc, EndLoc))
|
||||
if (ParseRegister(RegNo, StartLoc, EndLoc))
|
||||
return true;
|
||||
// Clear previous parse error and return correct expression.
|
||||
Parser.clearPendingErrors();
|
||||
Res = X86MCExpr::create(RegNo, Parser.getContext());
|
||||
return false;
|
||||
}
|
||||
|
||||
return false;
|
||||
return Parser.parsePrimaryExpr(Res, EndLoc);
|
||||
}
|
||||
|
||||
bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
# .noaltmacro returns the format into a regular macro handling.
|
||||
# The default mode is ".noaltmacro" as first test checks.
|
||||
|
||||
# CHECK: error: unknown token in expression
|
||||
# CHECK: error: expected immediate expression
|
||||
# CHECK-NEXT: addl $%(1%4), %eax
|
||||
.macro inner_percent arg
|
||||
addl $\arg, %eax
|
||||
|
|
@ -18,12 +18,12 @@ inner_percent %(1%4)
|
|||
.noaltmacro
|
||||
|
||||
# CHECK: multi_args_macro %(1+4-5) 1 %2+1
|
||||
# CHECK: error: unknown token in expression
|
||||
# CHECK: error: expected immediate expression
|
||||
# CHECK-NEXT: addl $%(1+4-5), %eax
|
||||
|
||||
|
||||
# CHECK: multi_args_macro %(1+4-5),1,%4%10
|
||||
# CHECK: error: unknown token in expression
|
||||
# CHECK: error: expected immediate expression
|
||||
# CHECK-NEXT: addl $%(1+4-5), %eax
|
||||
.macro multi_args_macro arg1 arg2 arg3
|
||||
label\arg1\arg2\arg3:
|
||||
|
|
|
|||
|
|
@ -118,3 +118,39 @@ mov (%rax,%eiz), %ebx
|
|||
// 32: error: register %riz is only available in 64-bit mode
|
||||
// 64: error: base register is 32-bit, but index register is not
|
||||
mov (%eax,%riz), %ebx
|
||||
|
||||
|
||||
// Parse errors from assembler parsing.
|
||||
|
||||
v_ecx = %ecx
|
||||
v_eax = %eax
|
||||
v_gs = %gs
|
||||
v_imm = 4
|
||||
$test = %ebx
|
||||
|
||||
// 32: 7: error: expected register here
|
||||
// 64: 7: error: expected register here
|
||||
mov 4(4), %eax
|
||||
|
||||
// 32: 7: error: expected register here
|
||||
// 64: 7: error: expected register here
|
||||
mov 5(v_imm), %eax
|
||||
|
||||
// 32: 7: error: invalid register name
|
||||
// 64: 7: error: invalid register name
|
||||
mov 6(%v_imm), %eax
|
||||
|
||||
// 32: 8: warning: scale factor without index register is ignored
|
||||
// 64: 8: warning: scale factor without index register is ignored
|
||||
mov 7(,v_imm), %eax
|
||||
|
||||
// 64: 6: error: expected immediate expression
|
||||
mov $%eax, %ecx
|
||||
|
||||
// 32: 6: error: expected immediate expression
|
||||
// 64: 6: error: expected immediate expression
|
||||
mov $v_eax, %ecx
|
||||
|
||||
// 32: error: unexpected token in argument list
|
||||
// 64: error: unexpected token in argument list
|
||||
mov v_ecx(%eax), %ecx
|
||||
|
|
|
|||
|
|
@ -61,3 +61,406 @@ foo:
|
|||
# CHECK: movl %gs:8, %eax
|
||||
movl %gs:8, %eax
|
||||
|
||||
# Make sure we handle parsing uses of variables assigned
|
||||
# to registers in operands.
|
||||
|
||||
v_ecx = %ecx
|
||||
v_eax = %eax
|
||||
v_gs = %gs
|
||||
v_imm = 4
|
||||
|
||||
#CHECK: movl %eax, %ecx
|
||||
movl %eax, v_ecx
|
||||
|
||||
#CHECK: movl $1, %gs:0
|
||||
movl $1, v_gs:(,)
|
||||
#CHECK: movl $1, %gs:(,%eax)
|
||||
movl $1, v_gs:(,%eax)
|
||||
#CHECK: movl $1, %gs:(,%eax,2)
|
||||
movl $1, v_gs:(,%eax,2)
|
||||
#CHECK: movl $1, %gs:(,%eax,4)
|
||||
movl $1, v_gs:(,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:(,%eax)
|
||||
movl $1, v_gs:(,v_eax)
|
||||
#CHECK: movl $1, %gs:(,%eax,2)
|
||||
movl $1, v_gs:(,v_eax,2)
|
||||
#CHECK: movl $1, %gs:(,%eax,4)
|
||||
movl $1, v_gs:(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:(%ecx)
|
||||
movl $1, v_gs:(%ecx)
|
||||
#CHECK: movl $1, %gs:(%ecx)
|
||||
movl $1, v_gs:(%ecx,)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax)
|
||||
movl $1, v_gs:(%ecx,%eax)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,2)
|
||||
movl $1, v_gs:(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,4)
|
||||
movl $1, v_gs:(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax)
|
||||
movl $1, v_gs:(%ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,2)
|
||||
movl $1, v_gs:(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,4)
|
||||
movl $1, v_gs:(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:(%ecx)
|
||||
movl $1, v_gs:(v_ecx)
|
||||
#CHECK: movl $1, %gs:(%ecx)
|
||||
movl $1, v_gs:(v_ecx,)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax)
|
||||
movl $1, v_gs:(v_ecx,%eax)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax)
|
||||
movl $1, v_gs:(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:4
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:4()
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:4(,)
|
||||
#CHECK: movl $1, %gs:4(,%eax)
|
||||
movl $1, v_gs:4(,%eax)
|
||||
#CHECK: movl $1, %gs:4(,%eax,2)
|
||||
movl $1, v_gs:4(,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(,%eax,4)
|
||||
movl $1, v_gs:4(,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(,%eax)
|
||||
movl $1, v_gs:4(,v_eax)
|
||||
#CHECK: movl $1, %gs:4(,%eax,2)
|
||||
movl $1, v_gs:4(,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(,%eax,4)
|
||||
movl $1, v_gs:4(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:4(%ecx)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:4(%ecx,)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:4(%ecx,%eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:4(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:4(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:4(%ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:4(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:4(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:4(v_ecx)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:4(v_ecx,)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:4(v_ecx,%eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:4(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:4(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:4(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:4(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:4(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:v_imm
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:v_imm()
|
||||
#CHECK: movl $1, %gs:4
|
||||
movl $1, v_gs:v_imm(,)
|
||||
#CHECK: movl $1, %gs:4(,%eax)
|
||||
movl $1, v_gs:v_imm(,%eax)
|
||||
#CHECK: movl $1, %gs:4(,%eax,2)
|
||||
movl $1, v_gs:v_imm(,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(,%eax,4)
|
||||
movl $1, v_gs:v_imm(,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(,%eax)
|
||||
movl $1, v_gs:v_imm(,v_eax)
|
||||
#CHECK: movl $1, %gs:4(,%eax,2)
|
||||
movl $1, v_gs:v_imm(,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(,%eax,4)
|
||||
movl $1, v_gs:v_imm(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:v_imm(%ecx)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:v_imm(%ecx,)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:v_imm(%ecx,%eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:v_imm(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:v_imm(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:v_imm(%ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:v_imm(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:v_imm(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:v_imm(v_ecx)
|
||||
#CHECK: movl $1, %gs:4(%ecx)
|
||||
movl $1, v_gs:v_imm(v_ecx,)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:v_imm(v_ecx,%eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:v_imm(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:v_imm(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax)
|
||||
movl $1, v_gs:v_imm(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,2)
|
||||
movl $1, v_gs:v_imm(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:4(%ecx,%eax,4)
|
||||
movl $1, v_gs:v_imm(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8
|
||||
movl $1, v_gs:(v_imm+4)
|
||||
#CHECK: movl $1, %gs:8
|
||||
movl $1, v_gs:(v_imm+4)()
|
||||
#CHECK: movl $1, %gs:8
|
||||
movl $1, v_gs:(v_imm+4)(,)
|
||||
#CHECK: movl $1, %gs:8(,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(,%eax)
|
||||
#CHECK: movl $1, %gs:8(,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(,%eax,2)
|
||||
#CHECK: movl $1, %gs:8(,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8(,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(,v_eax)
|
||||
#CHECK: movl $1, %gs:8(,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(,v_eax,2)
|
||||
#CHECK: movl $1, %gs:8(,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8(%ecx)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx)
|
||||
#CHECK: movl $1, %gs:8(%ecx)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,%eax)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8(%ecx)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx)
|
||||
#CHECK: movl $1, %gs:8(%ecx)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,%eax)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,2)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %gs:8(%ecx,%eax,4)
|
||||
movl $1, v_gs:(v_imm+4)(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:0
|
||||
movl $1, %fs:(,)
|
||||
#CHECK: movl $1, %fs:(,%eax)
|
||||
movl $1, %fs:(,%eax)
|
||||
#CHECK: movl $1, %fs:(,%eax,2)
|
||||
movl $1, %fs:(,%eax,2)
|
||||
#CHECK: movl $1, %fs:(,%eax,4)
|
||||
movl $1, %fs:(,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:(,%eax)
|
||||
movl $1, %fs:(,v_eax)
|
||||
#CHECK: movl $1, %fs:(,%eax,2)
|
||||
movl $1, %fs:(,v_eax,2)
|
||||
#CHECK: movl $1, %fs:(,%eax,4)
|
||||
movl $1, %fs:(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:(%ecx)
|
||||
movl $1, %fs:(%ecx)
|
||||
#CHECK: movl $1, %fs:(%ecx)
|
||||
movl $1, %fs:(%ecx,)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax)
|
||||
movl $1, %fs:(%ecx,%eax)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,2)
|
||||
movl $1, %fs:(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,4)
|
||||
movl $1, %fs:(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax)
|
||||
movl $1, %fs:(%ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,2)
|
||||
movl $1, %fs:(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,4)
|
||||
movl $1, %fs:(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:(%ecx)
|
||||
movl $1, %fs:(v_ecx)
|
||||
#CHECK: movl $1, %fs:(%ecx)
|
||||
movl $1, %fs:(v_ecx,)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax)
|
||||
movl $1, %fs:(v_ecx,%eax)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax)
|
||||
movl $1, %fs:(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:4
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:4()
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:4(,)
|
||||
#CHECK: movl $1, %fs:4(,%eax)
|
||||
movl $1, %fs:4(,%eax)
|
||||
#CHECK: movl $1, %fs:4(,%eax,2)
|
||||
movl $1, %fs:4(,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(,%eax,4)
|
||||
movl $1, %fs:4(,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(,%eax)
|
||||
movl $1, %fs:4(,v_eax)
|
||||
#CHECK: movl $1, %fs:4(,%eax,2)
|
||||
movl $1, %fs:4(,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(,%eax,4)
|
||||
movl $1, %fs:4(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:4(%ecx)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:4(%ecx,)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:4(%ecx,%eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:4(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:4(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:4(%ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:4(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:4(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:4(v_ecx)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:4(v_ecx,)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:4(v_ecx,%eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:4(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:4(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:4(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:4(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:4(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:v_imm
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:v_imm()
|
||||
#CHECK: movl $1, %fs:4
|
||||
movl $1, %fs:v_imm(,)
|
||||
#CHECK: movl $1, %fs:4(,%eax)
|
||||
movl $1, %fs:v_imm(,%eax)
|
||||
#CHECK: movl $1, %fs:4(,%eax,2)
|
||||
movl $1, %fs:v_imm(,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(,%eax,4)
|
||||
movl $1, %fs:v_imm(,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(,%eax)
|
||||
movl $1, %fs:v_imm(,v_eax)
|
||||
#CHECK: movl $1, %fs:4(,%eax,2)
|
||||
movl $1, %fs:v_imm(,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(,%eax,4)
|
||||
movl $1, %fs:v_imm(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:v_imm(%ecx)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:v_imm(%ecx,)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:v_imm(%ecx,%eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:v_imm(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:v_imm(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:v_imm(%ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:v_imm(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:v_imm(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:v_imm(v_ecx)
|
||||
#CHECK: movl $1, %fs:4(%ecx)
|
||||
movl $1, %fs:v_imm(v_ecx,)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:v_imm(v_ecx,%eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:v_imm(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:v_imm(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax)
|
||||
movl $1, %fs:v_imm(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,2)
|
||||
movl $1, %fs:v_imm(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:4(%ecx,%eax,4)
|
||||
movl $1, %fs:v_imm(v_ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8
|
||||
movl $1, %fs:(v_imm+4)
|
||||
#CHECK: movl $1, %fs:8
|
||||
movl $1, %fs:(v_imm+4)()
|
||||
#CHECK: movl $1, %fs:8
|
||||
movl $1, %fs:(v_imm+4)(,)
|
||||
#CHECK: movl $1, %fs:8(,%eax)
|
||||
movl $1, %fs:(v_imm+4)(,%eax)
|
||||
#CHECK: movl $1, %fs:8(,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(,%eax,2)
|
||||
#CHECK: movl $1, %fs:8(,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8(,%eax)
|
||||
movl $1, %fs:(v_imm+4)(,v_eax)
|
||||
#CHECK: movl $1, %fs:8(,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(,v_eax,2)
|
||||
#CHECK: movl $1, %fs:8(,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8(%ecx)
|
||||
movl $1, %fs:(v_imm+4)(%ecx)
|
||||
#CHECK: movl $1, %fs:8(%ecx)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,%eax)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(%ecx,v_eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8(%ecx)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx)
|
||||
#CHECK: movl $1, %fs:8(%ecx)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,%eax)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,%eax,2)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,%eax,v_imm)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,v_eax)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,2)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,v_eax,2)
|
||||
#CHECK: movl $1, %fs:8(%ecx,%eax,4)
|
||||
movl $1, %fs:(v_imm+4)(v_ecx,v_eax,v_imm)
|
||||
|
|
|
|||
Loading…
Reference in New Issue