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Use the function template getSubtarget off of the machine function, 

and use it in all locations.

llvm-svn: 227890
This commit is contained in:
Eric Christopher 2015-02-02 23:03:43 +00:00
parent 18cf8e018a
commit 6b6db77824
1 changed files with 10 additions and 13 deletions
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23
llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp
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@ -495,8 +495,8 @@ getUnderlyingObjects(const MachineInstr &MI,
// Replace Branch with the compact branch instruction.
Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB,
Iter Branch, DebugLoc DL) {
const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
MBB.getParent()->getSubtarget().getInstrInfo());
const MipsInstrInfo *TII =
MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
unsigned NewOpcode =
(((unsigned) Branch->getOpcode()) == Mips::BEQ) ? Mips::BEQZC_MM
@ -538,8 +538,7 @@ static int getEquivalentCallShort(int Opcode) {
/// We assume there is only one delay slot per delayed instruction.
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
const MipsSubtarget &STI =
static_cast<const MipsSubtarget &>(MBB.getParent()->getSubtarget());
const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
@ -623,8 +622,8 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
if (delayHasHazard(*I, RegDU, IM))
continue;
if (static_cast<const MipsSubtarget &>(MBB.getParent()->getSubtarget())
.isTargetNaCl()) {
const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
if (STI.isTargetNaCl()) {
// In NaCl, instructions that must be masked are forbidden in delay slots.
// We only check for loads, stores and SP changes. Calls, returns and
// branches are not checked because non-NaCl targets never put them in
@ -632,14 +631,12 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
unsigned AddrIdx;
if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) &&
baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) ||
I->modifiesRegister(Mips::SP,
TM.getSubtargetImpl()->getRegisterInfo()))
I->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
continue;
}
bool InMicroMipsMode = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode();
const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
TM.getSubtargetImpl()->getInstrInfo());
bool InMicroMipsMode = STI.inMicroMipsMode();
const MipsInstrInfo *TII = STI.getInstrInfo();
unsigned Opcode = (*Slot).getOpcode();
if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*I)) == 2 &&
(Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
@ -754,8 +751,8 @@ MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const {
std::pair<MipsInstrInfo::BranchType, MachineInstr *>
Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const {
const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
MBB.getParent()->getSubtarget().getInstrInfo());
const MipsInstrInfo *TII =
MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo();
MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr;
SmallVector<MachineInstr*, 2> BranchInstrs;
SmallVector<MachineOperand, 2> Cond;