forked from OSchip/llvm-project
parent
f7ee16f9e3
commit
6b42f2d8aa
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@ -256,10 +256,3 @@ def VSrc_64 : RegImmOperand<VS_64>;
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def VCSrc_32 : RegInlineOperand<VS_32>;
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def VCSrc_64 : RegInlineOperand<VS_64>;
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//===----------------------------------------------------------------------===//
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// SGPR and VGPR register classes
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//===----------------------------------------------------------------------===//
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def VSrc_128 : RegisterClass<"AMDGPU", [v4i32, v4f32], 128,
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(add VReg_128, SReg_128)>;
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