forked from OSchip/llvm-project
Don't allow per-register spill size and alignment.
These values were not used for anything. Spill size and alignment is a property of the register class, not the register. llvm-svn: 129906
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@ -32,17 +32,6 @@ class Register<string n> {
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string Namespace = "";
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string AsmName = n;
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// SpillSize - If this value is set to a non-zero value, it is the size in
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// bits of the spill slot required to hold this register. If this value is
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// set to zero, the information is inferred from any register classes the
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// register belongs to.
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int SpillSize = 0;
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// SpillAlignment - This value is used to specify the alignment required for
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// spilling the register. Like SpillSize, this should only be explicitly
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// specified if the register is not in a register class.
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int SpillAlignment = 0;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modify the aliased
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// registers.
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@ -29,7 +29,6 @@ namespace llvm {
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struct CodeGenRegister {
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Record *TheDef;
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const std::string &getName() const;
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unsigned DeclaredSpillSize, DeclaredSpillAlignment;
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unsigned EnumValue;
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unsigned CostPerUse;
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CodeGenRegister(Record *R);
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@ -170,8 +170,6 @@ void CodeGenTarget::ReadRegisters() const {
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}
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CodeGenRegister::CodeGenRegister(Record *R) : TheDef(R) {
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DeclaredSpillSize = R->getValueAsInt("SpillSize");
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DeclaredSpillAlignment = R->getValueAsInt("SpillAlignment");
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CostPerUse = R->getValueAsInt("CostPerUse");
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}
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