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[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot 

Differential Revision: https://reviews.llvm.org/D91730
This commit is contained in:
Craig Topper 2020-11-18 18:23:55 -08:00
parent bd106d7469
commit 6b0fc1f3c1
2 changed files with 23 additions and 10 deletions
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22
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
View File

@ -119,8 +119,13 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (I != MBB.end())
DL = I->getDebugLoc();
unsigned Opcode;
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
unsigned Opcode;
if (RISCV::GPRRegClass.hasSubClassEq(RC))
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
RISCV::SW : RISCV::SD;
@ -134,7 +139,8 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(Opcode))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
.addImm(0);
.addImm(0)
.addMemOperand(MMO);
}
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@ -146,8 +152,13 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (I != MBB.end())
DL = I->getDebugLoc();
unsigned Opcode;
MachineFunction *MF = MBB.getParent();
const MachineFrameInfo &MFI = MF->getFrameInfo();
MachineMemOperand *MMO = MF->getMachineMemOperand(
MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
unsigned Opcode;
if (RISCV::GPRRegClass.hasSubClassEq(RC))
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
RISCV::LW : RISCV::LD;
@ -158,7 +169,10 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
else
llvm_unreachable("Can't load this register from stack slot");
BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
BuildMI(MBB, I, DL, get(Opcode), DstReg)
.addFrameIndex(FI)
.addImm(0)
.addMemOperand(MMO);
}
void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,

11
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
View File

@ -222,14 +222,13 @@ define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: fld ft0, 8(sp)
; RV32I-NEXT: sw a1, 8(sp)
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: fld ft1, 8(sp)
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB5_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: fmv.d ft1, ft0
; RV32I-NEXT: sw a2, 12(sp)
; RV32I-NEXT: beqz a0, .LBB5_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: fld ft0, 8(sp)
; RV32I-NEXT: .LBB5_2: # %entry
; RV32I-NEXT: fsd ft1, 8(sp)
; RV32I-NEXT: fsd ft0, 8(sp)
; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw a1, 12(sp)
; RV32I-NEXT: addi sp, sp, 16