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[RISCV] Rename pcnt->cpop to match 0.93 bitmanip spec. 

This is the first of multiple patches to bring our 0.92
implementation up to 0.93.

Reviewed By: asb, frasercrmck

Differential Revision: https://reviews.llvm.org/D94568
This commit is contained in:
Craig Topper 2021-01-22 10:23:46 -08:00
parent 9d2796210f
commit 6aced6bf39
7 changed files with 21 additions and 21 deletions
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10
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
View File

@ -289,7 +289,7 @@ def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0010011>, "clz">,
Sched<[]>;
def CTZ : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0010011>, "ctz">,
Sched<[]>;
def PCNT : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "pcnt">,
def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0010011>, "cpop">,
Sched<[]>;
} // Predicates = [HasStdExtZbb]
@ -441,8 +441,8 @@ def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, RISCVOpcode<0b0011011>,
"clzw">, Sched<[]>;
def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, RISCVOpcode<0b0011011>,
"ctzw">, Sched<[]>;
def PCNTW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
"pcntw">, Sched<[]>;
def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, RISCVOpcode<0b0011011>,
"cpopw">, Sched<[]>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbc, IsRV64] in {
@ -772,7 +772,7 @@ def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
let Predicates = [HasStdExtZbb] in {
def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>;
def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
def : Pat<(ctpop GPR:$rs1), (CPOP GPR:$rs1)>;
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbb] in {
@ -948,7 +948,7 @@ def : Pat<(and (add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
(CLZW GPR:$rs1)>;
def : Pat<(cttz (or GPR:$rs1, (i64 0x100000000))),
(CTZW GPR:$rs1)>;
def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;
def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (CPOPW GPR:$rs1)>;
} // Predicates = [HasStdExtZbb, IsRV64]
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {

12
llvm/test/CodeGen/RISCV/rv32Zbb.ll
View File

@ -671,12 +671,12 @@ define i32 @ctpop_i32(i32 %a) nounwind {
;
; RV32IB-LABEL: ctpop_i32:
; RV32IB: # %bb.0:
; RV32IB-NEXT: pcnt a0, a0
; RV32IB-NEXT: cpop a0, a0
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: ctpop_i32:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: pcnt a0, a0
; RV32IBB-NEXT: cpop a0, a0
; RV32IBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1
@ -744,16 +744,16 @@ define i64 @ctpop_i64(i64 %a) nounwind {
;
; RV32IB-LABEL: ctpop_i64:
; RV32IB: # %bb.0:
; RV32IB-NEXT: pcnt a1, a1
; RV32IB-NEXT: pcnt a0, a0
; RV32IB-NEXT: cpop a1, a1
; RV32IB-NEXT: cpop a0, a0
; RV32IB-NEXT: add a0, a0, a1
; RV32IB-NEXT: mv a1, zero
; RV32IB-NEXT: ret
;
; RV32IBB-LABEL: ctpop_i64:
; RV32IBB: # %bb.0:
; RV32IBB-NEXT: pcnt a1, a1
; RV32IBB-NEXT: pcnt a0, a0
; RV32IBB-NEXT: cpop a1, a1
; RV32IBB-NEXT: cpop a0, a0
; RV32IBB-NEXT: add a0, a0, a1
; RV32IBB-NEXT: mv a1, zero
; RV32IBB-NEXT: ret

8
llvm/test/CodeGen/RISCV/rv64Zbb.ll
View File

@ -590,12 +590,12 @@ define signext i32 @ctpop_i32(i32 signext %a) nounwind {
;
; RV64IB-LABEL: ctpop_i32:
; RV64IB: # %bb.0:
; RV64IB-NEXT: pcntw a0, a0
; RV64IB-NEXT: cpopw a0, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: ctpop_i32:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: pcntw a0, a0
; RV64IBB-NEXT: cpopw a0, a0
; RV64IBB-NEXT: ret
%1 = call i32 @llvm.ctpop.i32(i32 %a)
ret i32 %1
@ -656,12 +656,12 @@ define i64 @ctpop_i64(i64 %a) nounwind {
;
; RV64IB-LABEL: ctpop_i64:
; RV64IB: # %bb.0:
; RV64IB-NEXT: pcnt a0, a0
; RV64IB-NEXT: cpop a0, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: ctpop_i64:
; RV64IBB: # %bb.0:
; RV64IBB-NEXT: pcnt a0, a0
; RV64IBB-NEXT: cpop a0, a0
; RV64IBB-NEXT: ret
%1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1

2
llvm/test/MC/RISCV/rv32zbb-invalid.s
View File

@ -19,7 +19,7 @@ clz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
# Too many operands
ctz t0, t1, t2 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
# Too many operands
pcnt t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
cpop t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
# Too many operands
sext.b t0, t1, t2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
# Too many operands

4
llvm/test/MC/RISCV/rv32zbb-valid.s
View File

@ -30,9 +30,9 @@ clz t0, t1
# CHECK-ASM-AND-OBJ: ctz t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x13,0x60]
ctz t0, t1
# CHECK-ASM-AND-OBJ: pcnt t0, t1
# CHECK-ASM-AND-OBJ: cpop t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x23,0x60]
pcnt t0, t1
cpop t0, t1
# CHECK-ASM-AND-OBJ: sext.b t0, t1
# CHECK-ASM: encoding: [0x93,0x12,0x43,0x60]
sext.b t0, t1

2
llvm/test/MC/RISCV/rv64zbb-invalid.s
View File

@ -37,4 +37,4 @@ clzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
# Too many operands
ctzw t0, t1, t2 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
# Too many operands
pcntw t0, t1, t2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
cpopw t0, t1, t2 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction

4
llvm/test/MC/RISCV/rv64zbb-valid.s
View File

@ -48,6 +48,6 @@ clzw t0, t1
# CHECK-ASM-AND-OBJ: ctzw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x13,0x60]
ctzw t0, t1
# CHECK-ASM-AND-OBJ: pcntw t0, t1
# CHECK-ASM-AND-OBJ: cpopw t0, t1
# CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
pcntw t0, t1
cpopw t0, t1