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[Hexagon] Remove trailing spaces, NFC 

llvm-svn: 318875
This commit is contained in:
Krzysztof Parzyszek 2017-11-22 20:43:00 +00:00
parent 24d6534038
commit 6acecc96ac
13 changed files with 16 additions and 16 deletions
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2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
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@ -1151,7 +1151,7 @@ SDValue HexagonTargetLowering::LowerFormalArguments(
EVT RegVT = VA.getLocVT();
if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
RegVT == MVT::i32 || RegVT == MVT::f32) {
unsigned VReg =
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);

4
llvm/lib/Target/Hexagon/HexagonRegisterInfo.td
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@ -63,7 +63,7 @@ let Namespace = "Hexagon" in {
// Rc - control registers
class Rc<bits<5> num, string n,
list<string> alt = [], list<Register> alias = []> :
list<string> alt = [], list<Register> alias = []> :
HexagonReg<num, n, alt, alias> {
let Num = num;
}
@ -285,7 +285,7 @@ def HvxQR : RegisterClass<"Hexagon", [VecI1], 512, (add Q0, Q1, Q2, Q3)> {
}
let Size = 32 in
def PredRegs : RegisterClass<"Hexagon",
def PredRegs : RegisterClass<"Hexagon",
[i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>;
let Size = 32 in

2
llvm/test/CodeGen/Hexagon/inline-asm-qv.ll
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@ -15,5 +15,5 @@ entry:
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
attributes #1 = { nounwind readnone }

2
llvm/test/CodeGen/Hexagon/intrinsics/xtype_fp.ll
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@ -342,7 +342,7 @@ declare float @llvm.hexagon.F2.sfimm.n(i32)
define float @F2_sfimm_n() {
%z = call float @llvm.hexagon.F2.sfimm.n(i32 0)
ret float %z
}
}
; CHECK: = sfmake(#0):neg
declare double @llvm.hexagon.F2.dfimm.p(i32)

2
llvm/test/CodeGen/Hexagon/mulh.ll
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@ -3,7 +3,7 @@
target triple = "hexagon"
; CHECK-LABEL: danny:
; CHECK: r{{[0-9]+}} = mpy(r0,r1)
; CHECK: r{{[0-9]+}} = mpy(r0,r1)
define i32 @danny(i32 %a0, i32 %a1) {
b2:
%v3 = sext i32 %a0 to i64

2
llvm/test/CodeGen/Hexagon/newvaluejump2.ll
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@ -1,6 +1,6 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hexagon-misched < %s \
; RUN: | FileCheck %s
; Check that we generate new value jump, both registers, with one
; Check that we generate new value jump, both registers, with one
; of the registers as new.
@Reg = common global i32 0, align 4

2
llvm/test/CodeGen/Hexagon/rdf-copy.ll
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@ -1,5 +1,5 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
;
;
; Check that
; {
; r1 = r0

2
llvm/test/CodeGen/Hexagon/split-const32-const64.ll
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@ -9,7 +9,7 @@
@lb = external global i64
; CHECK-LABEL: test1:
; CHECK-NOT: CONST32
; CHECK-NOT: CONST32
define void @test1() nounwind {
entry:
br label %block

4
llvm/test/MC/Disassembler/Hexagon/st.txt
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@ -243,7 +243,7 @@
0x03 0x40 0x45 0x85 0xab 0xf5 0x51 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) memh(r17++#10) = r21
0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab
0x03 0x40 0x45 0x85 0xaf 0xf5 0x51 0xab
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) memh(r17++#10) = r21
0x2b 0xf5 0x71 0xab
@ -326,7 +326,7 @@
# CHECK-NEXT: if (!p3.new) memw(r17+#84) = #31
0xab 0xdf 0x91 0x40
# CHECK: if (p3) memw(r17+#84) = r31
0xab 0xdf 0x91 0x44
0xab 0xdf 0x91 0x44
# CHECK: if (!p3) memw(r17+#84) = r31
0x03 0x40 0x45 0x85 0xab 0xdf 0x91 0x42
# CHECK: p3 = r5

2
llvm/test/MC/Hexagon/instructions/j.s
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@ -201,6 +201,6 @@ if (r17<=#0) jump:t 0
# Transfer and jump
# CHECK: 00 d5 09 16
{ r17 = #21 ; jump 0}
{ r17 = #21 ; jump 0 }
# CHECK: 00 c9 0d 17
{ r17 = r21 ; jump 0 }

4
llvm/test/MC/Hexagon/instructions/st.s
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@ -287,7 +287,7 @@ if (!p3) memh(r17++#10) = r21
{ p3 = r5
if (p3.new) memh(r17++#10) = r21 }
# CHECK: 03 40 45 85
# CHECK-NEXT: af f5 51 ab
# CHECK-NEXT: af f5 51 ab
{ p3 = r5
if (!p3.new) memh(r17++#10) = r21 }
# CHECK: 2b f5 71 ab
@ -390,7 +390,7 @@ if (!p3) memw(r17+#84)=#31
if (!p3.new) memw(r17+#84)=#31 }
# CHECK: ab df 91 40
if (p3) memw(r17+#84) = r31
# CHECK: ab df 91 44
# CHECK: ab df 91 44
if (!p3) memw(r17+#84) = r31
# CHECK: 03 40 45 85
# CHECK-NEXT: ab df 91 42

2
llvm/test/MC/Hexagon/test.s
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@ -1,4 +1,4 @@
#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s
{ vmem (r0 + #0) = v0
r0 = memw(r0) }
r0 = memw(r0) }

2
llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll
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@ -3,7 +3,7 @@
; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
; DISABLE-NOT: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
; DISABLE : = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]