maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RDF] Cache register units for reg masks instead of recalculating them 

llvm-svn: 300702
This commit is contained in:
Krzysztof Parzyszek 2017-04-19 15:10:09 +00:00
parent 5bfaf56ee5
commit 6aa3a3f00b
2 changed files with 29 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
llvm/lib/Target/Hexagon/RDFRegisters.cpp
View File

@ -69,6 +69,19 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
for (const MachineOperand &Op : In.operands())
if (Op.isRegMask())
RegMasks.insert(Op.getRegMask());
MaskInfos.resize(RegMasks.size()+1);
for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) {
BitVector PU(TRI.getNumRegUnits());
const uint32_t *MB = RegMasks.get(M);
for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) {
if (!(MB[i/32] & (1u << (i%32))))
continue;
for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U)
PU.set(*U);
}
MaskInfos[M].Units = PU.flip();
}
}
RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
@ -201,17 +214,8 @@ bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
// XXX SLOW
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (MB[i/32] & (1u << (i%32)))
continue;
if (hasAliasOf(RegisterRef(i, LaneBitmask::getAll())))
return true;
}
return false;
}
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
return Units.anyCommon(PRI.getMaskUnits(RR.Reg));
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
std::pair<uint32_t,LaneBitmask> P = *U;
@ -224,15 +228,8 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
// XXX SLOW
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (MB[i/32] & (1u << (i%32)))
continue;
if (!hasCoverOf(RegisterRef(i, LaneBitmask::getAll())))
return false;
}
return true;
BitVector T(PRI.getMaskUnits(RR.Reg));
return T.reset(Units).none();
}
for (MCRegUnitMaskIterator U(RR.Reg, &PRI.getTRI()); U.isValid(); ++U) {
@ -246,15 +243,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
BitVector PU(PRI.getTRI().getNumRegUnits()); // Preserved units.
const uint32_t *MB = PRI.getRegMaskBits(RR.Reg);
for (unsigned i = 1, e = PRI.getTRI().getNumRegs(); i != e; ++i) {
if (!(MB[i/32] & (1u << (i%32))))
continue;
for (MCRegUnitIterator U(i, &PRI.getTRI()); U.isValid(); ++U)
PU.set(*U);
}
Units |= PU.flip();
Units |= PRI.getMaskUnits(RR.Reg);
return *this;
}

13
llvm/lib/Target/Hexagon/RDFRegisters.h
View File

@ -51,6 +51,8 @@ namespace rdf {
return F - Map.begin() + 1;
}
uint32_t size() const { return Map.size(); }
typedef typename std::vector<T>::const_iterator const_iterator;
const_iterator begin() const { return Map.begin(); }
const_iterator end() const { return Map.end(); }
@ -107,6 +109,9 @@ namespace rdf {
RegisterRef getRefForUnit(uint32_t U) const {
return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask);
}
const BitVector &getMaskUnits(RegisterId MaskId) const {
return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
}
const TargetRegisterInfo &getTRI() const { return TRI; }
@ -118,11 +123,15 @@ namespace rdf {
RegisterId Reg = 0;
LaneBitmask Mask;
};
struct MaskInfo {
BitVector Units;
};
const TargetRegisterInfo &TRI;
IndexedSet<const uint32_t*> RegMasks;
std::vector<RegInfo> RegInfos;
std::vector<UnitInfo> UnitInfos;
IndexedSet<const uint32_t*> RegMasks;
std::vector<MaskInfo> MaskInfos;
bool aliasRR(RegisterRef RA, RegisterRef RB) const;
bool aliasRM(RegisterRef RR, RegisterRef RM) const;
@ -135,7 +144,7 @@ namespace rdf {
: Units(pri.getTRI().getNumRegUnits()), PRI(pri) {}
RegisterAggr(const RegisterAggr &RG) = default;
bool empty() const { return Units.empty(); }
bool empty() const { return Units.none(); }
bool hasAliasOf(RegisterRef RR) const;
bool hasCoverOf(RegisterRef RR) const;
static bool isCoverOf(RegisterRef RA, RegisterRef RB,