forked from OSchip/llvm-project
[ELF] AArch64 Errata fix, add missing files.
Forgot these from r319780 llvm-svn: 319781
This commit is contained in:
Peter Smith
parent
732cd8cbef
commit
6a954157dd
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@ -0,0 +1,489 @@
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//===- AArch64ErrataFix.cpp -----------------------------------------------===//
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//
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// The LLVM Linker
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This file implements Section Patching for the purpose of working around
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// errata in CPUs. The general principle is that an erratum sequence of one or
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// more instructions is detected in the instruction stream, one of the
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// instructions in the sequence is replaced with a branch to a patch sequence
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// of replacement instructions. At the end of the replacement sequence the
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// patch branches back to the instruction stream.
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// This technique is only suitable for fixing an erratum when:
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// - There is a set of necessary conditions required to trigger the erratum that
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// can be detected at static link time.
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// - There is a set of replacement instructions that can be used to remove at
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// least one of the necessary conditions that trigger the erratum.
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// - We can overwrite an instruction in the erratum sequence with a branch to
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// the replacement sequence.
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// - We can place the replacement sequence within range of the branch.
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// FIXME:
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// - At this stage the implementation only supports detection and not fixing,
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// this is sufficient to test the decode and recognition of the erratum
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// sequence.
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// - The implementation here only supports one patch, the AArch64 Cortex-53
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// errata 843419 that affects r0p0, r0p1, r0p2 and r0p4 versions of the core.
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// To keep the initial version simple there is no support for multiple
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// architectures or selection of different patches.
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//===----------------------------------------------------------------------===//
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#include "AArch64ErrataFix.h"
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#include "Config.h"
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#include "LinkerScript.h"
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#include "lld/Common/Memory.h"
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#include "OutputSections.h"
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#include "Relocations.h"
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#include "Strings.h"
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#include "SyntheticSections.h"
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#include "Target.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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using namespace llvm::ELF;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace lld;
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using namespace lld::elf;
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// Helper functions to identify instructions and conditions needed to trigger
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// the Cortex-A53-843419 erratum.
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// ADRP
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// | 1 | immlo (2) | 1 | 0 0 0 0 | immhi (19) | Rd (5) |
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static bool isADRP(uint32_t Instr) {
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return (Instr & 0x9f000000) == 0x90000000;
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}
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// Load and store bit patterns from ARMv8-A ARM ARM.
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// Instructions appear in order of appearance starting from table in
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// C4.1.3 Loads and Stores.
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// All loads and stores have 1 (at bit postion 27), (0 at bit position 25).
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// | op0 x op1 (2) | 1 op2 0 op3 (2) | x | op4 (5) | xxxx | op5 (2) | x (10) |
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static bool isLoadStoreClass(uint32_t Instr) {
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return (Instr & 0x0a000000) == 0x08000000;
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}
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// LDN/STN multiple no offset
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// | 0 Q 00 | 1100 | 0 L 00 | 0000 | opcode (4) | size (2) | Rn (5) | Rt (5) |
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// LDN/STN multiple post-indexed
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// | 0 Q 00 | 1100 | 1 L 0 | Rm (5)| opcode (4) | size (2) | Rn (5) | Rt (5) |
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// L == 0 for stores.
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// Utility routine to decode opcode field of LDN/STN multiple structure
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// instructions to find the ST1 instructions.
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// opcode == 0010 ST1 4 registers.
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// opcode == 0110 ST1 3 registers.
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// opcode == 0111 ST1 1 register.
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// opcode == 1010 ST1 2 registers.
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static bool isST1MultipleOpcode(uint32_t Instr) {
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return (Instr & 0x0000f000) == 0x00002000 ||
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(Instr & 0x0000f000) == 0x00006000 ||
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(Instr & 0x0000f000) == 0x00007000 ||
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(Instr & 0x0000f000) == 0x0000a000;
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}
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static bool isST1Multiple(uint32_t Instr) {
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return (Instr & 0xbfff0000) == 0x0c000000 && isST1MultipleOpcode(Instr);
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}
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// Writes to Rn (writeback).
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static bool isST1MultiplePost(uint32_t Instr) {
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return (Instr & 0xbfe00000) == 0x0c800000 && isST1MultipleOpcode(Instr);
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}
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// LDN/STN single no offset
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// | 0 Q 00 | 1101 | 0 L R 0 | 0000 | opc (3) S | size (2) | Rn (5) | Rt (5)|
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// LDN/STN single post-indexed
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// | 0 Q 00 | 1101 | 1 L R | Rm (5) | opc (3) S | size (2) | Rn (5) | Rt (5)|
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// L == 0 for stores
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// Utility routine to decode opcode field of LDN/STN single structure
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// instructions to find the ST1 instructions.
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// R == 0 for ST1 and ST3, R == 1 for ST2 and ST4.
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// opcode == 000 ST1 8-bit.
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// opcode == 010 ST1 16-bit.
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// opcode == 100 ST1 32 or 64-bit (Size determines which).
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static bool isST1SingleOpcode(uint32_t Instr) {
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return (Instr & 0x0040e000) == 0x00000000 ||
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(Instr & 0x0040e000) == 0x00004000 ||
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(Instr & 0x0040e000) == 0x00008000;
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}
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static bool isST1Single(uint32_t Instr) {
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return (Instr & 0xbfff0000) == 0x0d000000 && isST1SingleOpcode(Instr);
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}
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// Writes to Rn (writeback).
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static bool isST1SinglePost(uint32_t Instr) {
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return (Instr & 0xbfe00000) == 0x0d800000 && isST1SingleOpcode(Instr);
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}
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static bool isST1(uint32_t Instr) {
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return isST1Multiple(Instr) || isST1MultiplePost(Instr) ||
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isST1Single(Instr) || isST1SinglePost(Instr);
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}
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// Load/store exclusive
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// | size (2) 00 | 1000 | o2 L o1 | Rs (5) | o0 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for Stores.
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static bool isLoadStoreExclusive(uint32_t Instr) {
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return (Instr & 0x3f000000) == 0x08000000;
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}
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static bool isLoadExclusive(uint32_t Instr) {
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return (Instr & 0x3f400000) == 0x08400000;
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}
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// Load register literal
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// | opc (2) 01 | 1 V 00 | imm19 | Rt (5) |
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static bool isLoadLiteral(uint32_t Instr) {
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return (Instr & 0x3b000000) == 0x18000000;
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}
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// Load/store no-allocate pair
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// (offset)
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// | opc (2) 10 | 1 V 00 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for stores.
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// Never writes to register
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static bool isSTNP(uint32_t Instr) {
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return (Instr & 0x3bc00000) == 0x28000000;
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}
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// Load/store register pair
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// (post-indexed)
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// | opc (2) 10 | 1 V 00 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// L == 0 for stores, V == 0 for Scalar, V == 1 for Simd/FP
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// Writes to Rn.
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static bool isSTPPost(uint32_t Instr) {
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return (Instr & 0x3bc00000) == 0x28800000;
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}
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// (offset)
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// | opc (2) 10 | 1 V 01 | 0 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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static bool isSTPOffset(uint32_t Instr) {
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return (Instr & 0x3bc00000) == 0x29000000;
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}
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// (pre-index)
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// | opc (2) 10 | 1 V 01 | 1 L | imm7 | Rt2 (5) | Rn (5) | Rt (5) |
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// Writes to Rn.
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static bool isSTPPre(uint32_t Instr) {
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return (Instr & 0x3bc00000) == 0x29800000;
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}
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static bool isSTP(uint32_t Instr) {
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return isSTPPost(Instr) || isSTPOffset(Instr) || isSTPPre(Instr);
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}
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// Load/store register (unscaled immediate)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 00 | Rn (5) | Rt (5) |
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// V == 0 for Scalar, V == 1 for Simd/FP.
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static bool isLoadStoreUnscaled(uint32_t Instr) {
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return (Instr & 0x3b000c00) == 0x38000000;
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}
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// Load/store register (immediate post-indexed)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 01 | Rn (5) | Rt (5) |
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static bool isLoadStoreImmediatePost(uint32_t Instr) {
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return (Instr & 0x3b200c00) == 0x38000400;
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}
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// Load/store register (unprivileged)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 10 | Rn (5) | Rt (5) |
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static bool isLoadStoreUnpriv(uint32_t Instr) {
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return (Instr & 0x3b200c00) == 0x38000800;
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}
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// Load/store register (immediate pre-indexed)
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// | size (2) 11 | 1 V 00 | opc (2) 0 | imm9 | 11 | Rn (5) | Rt (5) |
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static bool isLoadStoreImmediatePre(uint32_t Instr) {
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return (Instr & 0x3b200c00) == 0x38000c00;
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}
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// Load/store register (register offset)
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// | size (2) 11 | 1 V 00 | opc (2) 1 | Rm (5) | option (3) S | 10 | Rn | Rt |
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static bool isLoadStoreRegisterOff(uint32_t Instr) {
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return (Instr & 0x3b200c00) == 0x38200800;
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}
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// Load/store register (unsigned immediate)
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// | size (2) 11 | 1 V 01 | opc (2) | imm12 | Rn (5) | Rt (5) |
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static bool isLoadStoreRegisterUnsigned(uint32_t Instr) {
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return (Instr & 0x3b000000) == 0x39000000;
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}
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// Rt is always in bit position 0 - 4.
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static uint32_t getRt(uint32_t Instr) { return (Instr & 0x1f); }
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// Rn is always in bit position 5 - 9.
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static uint32_t getRn(uint32_t Instr) { return (Instr >> 5) & 0x1f; }
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// C4.1.2 Branches, Exception Generating and System instructions
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// | op0 (3) 1 | 01 op1 (4) | x (22) |
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// op0 == 010 101 op1 == 0xxx Conditional Branch.
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// op0 == 110 101 op1 == 1xxx Unconditional Branch Register.
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// op0 == x00 101 op1 == xxxx Unconditional Branch immediate.
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// op0 == x01 101 op1 == 0xxx Compare and branch immediate.
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// op0 == x01 101 op1 == 1xxx Test and branch immediate.
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static bool isBranch(uint32_t Instr) {
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return ((Instr & 0xfe000000) == 0xd6000000) || // Cond branch.
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((Instr & 0xfe000000) == 0x54000000) || // Uncond branch reg.
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((Instr & 0x7c000000) == 0x14000000) || // Uncond branch imm.
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((Instr & 0x7c000000) == 0x34000000); // Compare and test branch.
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}
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static bool isV8SingleRegisterNonStructureLoadStore(uint32_t Instr) {
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return isLoadStoreUnscaled(Instr) || isLoadStoreImmediatePost(Instr) ||
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isLoadStoreUnpriv(Instr) || isLoadStoreImmediatePre(Instr) ||
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isLoadStoreRegisterOff(Instr) || isLoadStoreRegisterUnsigned(Instr);
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}
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// Note that this function refers to v8.0 only and does not include the
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// additional load and store instructions added for in later revisions of
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// the architecture such as the Atomic memory operations introduced
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// in v8.1.
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static bool isV8NonStructureLoad(uint32_t Instr) {
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if (isLoadExclusive(Instr))
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return true;
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if (isLoadLiteral(Instr))
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return true;
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else if (isV8SingleRegisterNonStructureLoadStore(Instr)) {
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// For Load and Store single register, Loads are derived from a
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// combination of the Size, V and Opc fields.
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uint32_t Size = (Instr >> 30) & 0xff;
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uint32_t V = (Instr >> 26) & 0x1;
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uint32_t Opc = (Instr >> 22) & 0x3;
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// For the load and store instructions that we are decoding.
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// Opc == 0 are all stores.
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// Opc == 1 with a couple of exceptions are loads. The exceptions are:
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// Size == 00 (0), V == 1, Opc == 10 (2) which is a store and
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// Size == 11 (3), V == 0, Opc == 10 (2) which is a prefetch.
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return Opc != 0 && !(Size == 0 && V == 1 && Opc == 2) &&
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!(Size == 3 && V == 0 && Opc == 2);
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}
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return false;
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}
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// The following decode instructions are only complete up to the instructions
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// needed for errata 843419.
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// Instruction with writeback updates the index register after the load/store.
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static bool hasWriteback(uint32_t Instr) {
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return isLoadStoreImmediatePre(Instr) || isLoadStoreImmediatePost(Instr) ||
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isSTPPre(Instr) || isSTPPost(Instr) || isST1SinglePost(Instr) ||
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isST1MultiplePost(Instr);
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}
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// For the load and store class of instructions, a load can write to the
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// destination register, a load and a store can write to the base register when
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// the instruction has writeback.
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static bool doesLoadStoreWriteToReg(uint32_t Instr, uint32_t Reg) {
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return (isV8NonStructureLoad(Instr) && getRt(Instr) == Reg) ||
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(hasWriteback(Instr) && getRn(Instr) == Reg);
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}
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// Scanner for Cortex-A53 errata 843419
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// Full details are available in the Cortex A53 MPCore revision 0 Software
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// Developers Errata Notice (ARM-EPM-048406).
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//
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// The instruction sequence that triggers the erratum is common in compiled
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// AArch64 code, however it is sensitive to the offset of the sequence within
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// a 4k page. This means that by scanning and fixing the patch after we have
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// assigned addresses we only need to disassemble and fix instances of the
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// sequence in the range of affected offsets.
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//
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// In summary the erratum conditions are a series of 4 instructions:
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// 1.) An ADRP instruction that writes to register Rn with low 12 bits of
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// address of instruction either 0xff8 or 0xffc.
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// 2.) A load or store instruction that can be:
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// - A single register load or store, of either integer or vector registers.
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// - An STP or STNP, of either integer or vector registers.
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// - An Advanced SIMD ST1 store instruction.
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// - Must not write to Rn, but may optionally read from it.
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// 3.) An optional instruction that is not a branch and does not write to Rn.
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// 4.) A load or store from the Load/store register (unsigned immediate) class
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// that uses Rn as the base address register.
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//
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// Note that we do not attempt to scan for Sequence 2 as described in the
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// Software Developers Errata Notice as this has been assessed to be extremely
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// unlikely to occur in compiled code. This matches gold and ld.bfd behavior.
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// Return true if the Instruction sequence Adrp, Instr2, and Instr4 match
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// the erratum sequence. The Adrp, Instr2 and Instr4 correspond to 1.), 2.),
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// and 4.) in the Scanner for Cortex-A53 errata comment above.
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static bool is843419ErratumSequence(uint32_t Instr1, uint32_t Instr2,
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uint32_t Instr4) {
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if (!isADRP(Instr1))
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return false;
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uint32_t Rn = getRt(Instr1);
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return isLoadStoreClass(Instr2) &&
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(isLoadStoreExclusive(Instr2) || isLoadLiteral(Instr2) ||
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isV8SingleRegisterNonStructureLoadStore(Instr2) || isSTP(Instr2) ||
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isSTNP(Instr2) || isST1(Instr2)) &&
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!doesLoadStoreWriteToReg(Instr2, Rn) &&
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isLoadStoreRegisterUnsigned(Instr4) && getRn(Instr4) == Rn;
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}
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static void report843419Fix(uint64_t AdrpAddr) {
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if (!Config->Verbose)
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return;
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message("detected cortex-a53-843419 erratum sequence starting at " +
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utohexstr(AdrpAddr) + " in unpatched output.");
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}
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// Scan the instruction sequence starting at Offset Off from the base of
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// InputSection IS. We update Off in this function rather than in the caller as
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// we can skip ahead much further into the section when we know how many
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// instructions we've scanned.
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// Return the offset of the load or store instruction in IS that we want to
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// patch or 0 if no patch required.
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static uint64_t scanCortexA53Errata843419(InputSection *IS, uint64_t &Off,
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uint64_t Limit) {
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uint64_t ISAddr = IS->getParent()->Addr + IS->OutSecOff;
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// Advance Off so that (ISAddr + Off) modulo 0x1000 is at least 0xff8.
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uint64_t InitialPageOff = (ISAddr + Off) & 0xfff;
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if (InitialPageOff < 0xff8)
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Off += 0xff8 - InitialPageOff;
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bool OptionalAllowed = Limit - Off > 12;
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if (Off >= Limit || Limit - Off < 12) {
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// Need at least 3 4-byte sized instructions to trigger erratum.
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Off = Limit;
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return 0;
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}
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uint64_t PatchOff = 0;
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const uint8_t *Buf = IS->Data.begin();
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const uint32_t *InstBuf = reinterpret_cast<const uint32_t *>(Buf + Off);
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uint32_t Instr1 = *InstBuf++;
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uint32_t Instr2 = *InstBuf++;
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uint32_t Instr3 = *InstBuf++;
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if (is843419ErratumSequence(Instr1, Instr2, Instr3)) {
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PatchOff = Off + 8;
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} else if (OptionalAllowed && !isBranch(Instr3)) {
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uint32_t Instr4 = *InstBuf++;
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if (is843419ErratumSequence(Instr1, Instr2, Instr4))
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PatchOff = Off + 12;
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}
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if (((ISAddr + Off) & 0xfff) == 0xff8)
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Off += 4;
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else
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Off += 0xffc;
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return PatchOff;
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}
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// The AArch64 ABI permits data in executable sections. We must avoid scanning
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// this data as if it were instructions to avoid false matches.
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// The ABI Section 4.5.4 Mapping symbols; defines local symbols that describe
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// half open intervals [Symbol Value, Next Symbol Value) of code and data
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// within sections. If there is no next symbol then the half open interval is
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// [Symbol Value, End of section). The type, code or data, is determined by the
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// mapping symbol name, $x for code, $d for data.
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std::map<InputSection *,
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std::vector<const Defined *>> static makeAArch64SectionMap() {
|
||||
std::map<InputSection *, std::vector<const Defined *>> SectionMap;
|
||||
auto IsCodeMapSymbol = [](const Symbol *B) {
|
||||
return B->getName() == "$x" || B->getName().startswith("$x.");
|
||||
};
|
||||
auto IsDataMapSymbol = [](const Symbol *B) {
|
||||
return B->getName() == "$d" || B->getName().startswith("$d.");
|
||||
};
|
||||
|
||||
// Collect mapping symbols for every executable InputSection.
|
||||
for (InputFile *File : ObjectFiles) {
|
||||
auto *F = cast<ObjFile<ELF64LE>>(File);
|
||||
for (Symbol *B : F->getLocalSymbols()) {
|
||||
auto *Def = dyn_cast<Defined>(B);
|
||||
if (!Def)
|
||||
continue;
|
||||
if (!IsCodeMapSymbol(Def) && !IsDataMapSymbol(Def))
|
||||
continue;
|
||||
if (auto *Sec = dyn_cast<InputSection>(Def->Section))
|
||||
if (Sec->Flags & SHF_EXECINSTR)
|
||||
SectionMap[Sec].push_back(Def);
|
||||
}
|
||||
}
|
||||
// For each InputSection make sure the mapping symbols are in sorted in
|
||||
// ascending order and free from consecutive runs of mapping symbols with
|
||||
// the same type. For example we must remove the redundant $d.1 from $x.0
|
||||
// $d.0 $d.1 $x.1.
|
||||
for (auto &KV : SectionMap) {
|
||||
std::vector<const Defined *> &MapSyms = KV.second;
|
||||
if (MapSyms.size() <= 1)
|
||||
continue;
|
||||
std::stable_sort(
|
||||
MapSyms.begin(), MapSyms.end(),
|
||||
[](const Defined *A, const Defined *B) { return A->Value < B->Value; });
|
||||
MapSyms.erase(
|
||||
std::unique(MapSyms.begin(), MapSyms.end(),
|
||||
[=](const Defined *A, const Defined *B) {
|
||||
return (IsCodeMapSymbol(A) && IsCodeMapSymbol(B)) ||
|
||||
(IsDataMapSymbol(A) && IsDataMapSymbol(B));
|
||||
}),
|
||||
MapSyms.end());
|
||||
}
|
||||
return SectionMap;
|
||||
}
|
||||
|
||||
static void scanInputSectionDescription(std::vector<const Defined *> &MapSyms,
|
||||
InputSection *IS) {
|
||||
// Use SectionMap to make sure we only scan code and not inline data.
|
||||
// We have already sorted MapSyms in ascending order and removed
|
||||
// consecutive mapping symbols of the same type. Our range of
|
||||
// executable instructions to scan is therefore [CodeSym->Value,
|
||||
// DataSym->Value) or [CodeSym->Value, section size).
|
||||
auto CodeSym = llvm::find_if(MapSyms, [&](const Defined *MS) {
|
||||
return MS->getName().startswith("$x");
|
||||
});
|
||||
|
||||
while (CodeSym != MapSyms.end()) {
|
||||
auto DataSym = std::next(CodeSym);
|
||||
uint64_t Off = (*CodeSym)->Value;
|
||||
uint64_t Limit =
|
||||
(DataSym == MapSyms.end()) ? IS->Data.size() : (*DataSym)->Value;
|
||||
|
||||
while (Off < Limit) {
|
||||
uint64_t StartAddr = IS->getParent()->Addr + IS->OutSecOff + Off;
|
||||
if (scanCortexA53Errata843419(IS, Off, Limit))
|
||||
report843419Fix(StartAddr);
|
||||
}
|
||||
if (DataSym == MapSyms.end())
|
||||
break;
|
||||
CodeSym = std::next(DataSym);
|
||||
}
|
||||
}
|
||||
|
||||
// Scan all the executable code in an AArch64 link to detect the Cortex-A53
|
||||
// erratum 843419.
|
||||
// FIXME: The current implementation only scans for the erratum sequence, it
|
||||
// does not attempt to fix it.
|
||||
void lld::elf::reportA53Errata843419Fixes() {
|
||||
std::map<InputSection *, std::vector<const Defined *>> SectionMap =
|
||||
makeAArch64SectionMap();
|
||||
|
||||
for (OutputSection *OS : OutputSections) {
|
||||
if (!(OS->Flags & SHF_ALLOC) || !(OS->Flags & SHF_EXECINSTR))
|
||||
continue;
|
||||
for (BaseCommand *BC : OS->SectionCommands)
|
||||
if (auto *ISD = dyn_cast<InputSectionDescription>(BC)) {
|
||||
for (InputSection *IS : ISD->Sections) {
|
||||
// LLD doesn't use the erratum sequence in SyntheticSections.
|
||||
if (isa<SyntheticSection>(IS))
|
||||
continue;
|
||||
scanInputSectionDescription(SectionMap[IS], IS);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
//===- AArch64ErrataFix.h ---------------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Linker
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLD_ELF_AARCH64ERRATAFIX_H
|
||||
#define LLD_ELF_AARCH64ERRATAFIX_H
|
||||
|
||||
#include "lld/Common/LLVM.h"
|
||||
|
||||
namespace lld {
|
||||
namespace elf {
|
||||
|
||||
class OutputSection;
|
||||
void reportA53Errata843419Fixes();
|
||||
|
||||
} // namespace elf
|
||||
} // namespace lld
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue