forked from OSchip/llvm-project
[PowerPC] Keep vector int to fp conversions in vector domain
At present a v2i16 -> v2f64 convert is implemented by extracts to scalar, scalar converts, and merge back into a vector. Use vector converts instead, with the int data permuted into the proper position and extended if necessary. Patch by RolandF. Differential revision: https://reviews.llvm.org/D53346 llvm-svn: 345361
This commit is contained in:
Nemanja Ivanovic
parent
98ac9984b0
commit
6a74bfba20
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@ -792,6 +792,9 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
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setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
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setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom);
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setOperationAction(ISD::FNEG, MVT::v4f32, Legal);
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setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
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setOperationAction(ISD::FABS, MVT::v4f32, Legal);
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@ -7265,10 +7268,75 @@ SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
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return FP;
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}
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static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) {
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EVT VecVT = Vec.getValueType();
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assert(VecVT.isVector() && "Expected a vector type.");
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assert(VecVT.getSizeInBits() < 128 && "Vector is already full width.");
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EVT EltVT = VecVT.getVectorElementType();
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unsigned WideNumElts = 128 / EltVT.getSizeInBits();
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EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);
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unsigned NumConcat = WideNumElts / VecVT.getVectorNumElements();
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SmallVector<SDValue, 16> Ops(NumConcat);
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Ops[0] = Vec;
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SDValue UndefVec = DAG.getUNDEF(VecVT);
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for (unsigned i = 1; i < NumConcat; ++i)
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Ops[i] = UndefVec;
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return DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, Ops);
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}
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SDValue PPCTargetLowering::LowerINT_TO_FPVector(SDValue Op,
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SelectionDAG &DAG,
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const SDLoc &dl) const {
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unsigned Opc = Op.getOpcode();
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assert((Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP) &&
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"Unexpected conversion type");
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assert(Op.getValueType() == MVT::v2f64 && "Supports v2f64 only.");
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// CPU's prior to P9 don't have a way to sign-extend in vectors.
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bool SignedConv = Opc == ISD::SINT_TO_FP;
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if (SignedConv && !Subtarget.hasP9Altivec())
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return SDValue();
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SDValue Wide = widenVec(DAG, Op.getOperand(0), dl);
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EVT WideVT = Wide.getValueType();
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unsigned WideNumElts = WideVT.getVectorNumElements();
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SmallVector<int, 16> ShuffV;
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for (unsigned i = 0; i < WideNumElts; ++i)
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ShuffV.push_back(i + WideNumElts);
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if (Subtarget.isLittleEndian()) {
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ShuffV[0] = 0;
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ShuffV[WideNumElts / 2] = 1;
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}
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else {
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ShuffV[WideNumElts / 2 - 1] = 0;
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ShuffV[WideNumElts - 1] = 1;
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}
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SDValue ShuffleSrc2 = SignedConv ? DAG.getUNDEF(WideVT) :
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DAG.getConstant(0, dl, WideVT);
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SDValue Arrange = DAG.getVectorShuffle(WideVT, dl, Wide, ShuffleSrc2, ShuffV);
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unsigned ExtendOp = SignedConv ? (unsigned) PPCISD::SExtVElems :
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(unsigned) ISD::BITCAST;
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SDValue Extend = DAG.getNode(ExtendOp, dl, MVT::v2i64, Arrange);
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return DAG.getNode(Opc, dl, Op.getValueType(), Extend);
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}
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SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc dl(Op);
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if (Op.getValueType() == MVT::v2f64 &&
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Op.getOperand(0).getValueType() == MVT::v2i16)
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return LowerINT_TO_FPVector(Op, DAG, dl);
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// Conversions to f128 are legal.
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if (EnableQuadPrecision && (Op.getValueType() == MVT::f128))
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return Op;
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@ -927,6 +927,9 @@ namespace llvm {
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SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
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const SDLoc &dl) const;
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SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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const SDLoc &dl) const;
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SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
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SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
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@ -0,0 +1,192 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-P8
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-P9
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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define void @test8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
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%1 = uitofp <8 x i16> %0 to <8 x double>
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store <8 x double> %1, <8 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: @test8
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: xvcvuxddp
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; CHECK-P9: xvcvuxddp
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; CHECK-P9: xvcvuxddp
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; CHECK-P9: xvcvuxddp
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; CHECK-P8-LABEL: @test8
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; CHECK-P8: vperm
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; CHECK-P8: vperm
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; CHECK-P8: vperm
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; CHECK-P8: vperm
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; CHECK-P8: xvcvuxddp
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; CHECK-P8: xvcvuxddp
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; CHECK-P8: xvcvuxddp
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; CHECK-P8: xvcvuxddp
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}
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define void @test4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
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%1 = uitofp <4 x i16> %0 to <4 x double>
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store <4 x double> %1, <4 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: @test4
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: xvcvuxddp
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; CHECK-P9: xvcvuxddp
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; CHECK-P8-LABEL: @test4
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; CHECK-P8: vperm
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; CHECK-P8: vperm
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; CHECK-P8: xvcvuxddp
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; CHECK-P8: xvcvuxddp
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}
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define void @test2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
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%1 = uitofp <2 x i16> %0 to <2 x double>
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store <2 x double> %1, <2 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: .LCPI2_0:
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 30
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; CHECK-P9-NEXT: .byte 13
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; CHECK-P9-NEXT: .byte 12
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; CHECK-P9-NEXT: .byte 11
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; CHECK-P9-NEXT: .byte 10
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; CHECK-P9-NEXT: .byte 9
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; CHECK-P9-NEXT: .byte 8
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; CHECK-P9-NEXT: .byte 29
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; CHECK-P9-NEXT: .byte 28
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; CHECK-P9-NEXT: .byte 5
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; CHECK-P9-NEXT: .byte 4
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; CHECK-P9-NEXT: .byte 3
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; CHECK-P9-NEXT: .byte 2
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; CHECK-P9-NEXT: .byte 1
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; CHECK-P9-NEXT: .byte 0
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; CHECK-P9: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0@toc@l
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; CHECK-P9: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
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; CHECK-P9: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
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; CHECK-P9: xvcvuxddp {{vs[0-9]+}}, [[REG3]]
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; CHECK-P8-LABEL: @test2
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; CHECK-P8: vperm [[REG1:v[0-9]+]]
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; CHECK-P8: xvcvuxddp {{vs[0-9]+}}, [[REG1]]
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; CHECK-BE-LABEL: .LCPI2_0:
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; CHECK-BE-NEXT: .byte 16
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; CHECK-BE-NEXT: .byte 17
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; CHECK-BE-NEXT: .byte 18
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; CHECK-BE-NEXT: .byte 19
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; CHECK-BE-NEXT: .byte 20
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; CHECK-BE-NEXT: .byte 21
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 1
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; CHECK-BE-NEXT: .byte 24
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; CHECK-BE-NEXT: .byte 25
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; CHECK-BE-NEXT: .byte 26
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; CHECK-BE-NEXT: .byte 27
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; CHECK-BE-NEXT: .byte 28
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; CHECK-BE-NEXT: .byte 29
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; CHECK-BE-NEXT: .byte 2
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; CHECK-BE-NEXT: .byte 3
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; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI2_0@toc@l
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; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
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; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
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; CHECK-BE: xvcvuxddp {{vs[0-9]+}}, [[REG3]]
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}
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define void @stest8(<8 x double>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
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%1 = sitofp <8 x i16> %0 to <8 x double>
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store <8 x double> %1, <8 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: @stest8
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vextsh2d
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; CHECK-P9: vextsh2d
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; CHECK-P9: vextsh2d
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; CHECK-P9: vextsh2d
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; CHECK-P9: xvcvsxddp
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; CHECK-P9: xvcvsxddp
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; CHECK-P9: xvcvsxddp
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; CHECK-P9: xvcvsxddp
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}
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define void @stest4(<4 x double>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
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%1 = sitofp <4 x i16> %0 to <4 x double>
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store <4 x double> %1, <4 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: @stest4
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; CHECK-P9: vperm
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; CHECK-P9: vperm
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; CHECK-P9: vextsh2d
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; CHECK-P9: vextsh2d
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; CHECK-P9: xvcvsxddp
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; CHECK-P9: xvcvsxddp
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}
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define void @stest2(<2 x double>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
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entry:
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%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
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%1 = sitofp <2 x i16> %0 to <2 x double>
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store <2 x double> %1, <2 x double>* %Sink, align 16
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ret void
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; CHECK-P9-LABEL: .LCPI5_0:
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 30
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 29
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; CHECK-P9-NEXT: .byte 28
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9-NEXT: .byte 31
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; CHECK-P9: vperm [[REG1:v[0-9]+]]
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; CHECK-P9: vextsh2d [[REG2:v[0-9]+]], [[REG1]]
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; CHECK-P9: xvcvsxddp {{vs[0-9]+}}, [[REG2]]
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; CHECK-BE-LABEL: .LCPI5_0:
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 1
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 0
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; CHECK-BE-NEXT: .byte 2
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; CHECK-BE-NEXT: .byte 3
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; CHECK-BE: addi [[REG1:r[0-9]+]], {{r[0-9]+}}, .LCPI5_0@toc@l
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; CHECK-BE: lxvx [[REG2:v[0-9]+]], 0, [[REG1]]
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; CHECK-BE: vperm [[REG3:v[0-9]+]], {{v[0-9]+}}, {{v[0-9]+}}, [[REG2]]
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; CHECK-BE: vextsh2d [[REG4:v[0-9]+]], [[REG3]]
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; CHECK-BE: xvcvsxddp {{vs[0-9]+}}, [[REG4]]
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}
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