forked from OSchip/llvm-project
AMDGPU/GlobalISel: Commit test changes I forgot to squash
These should have been in ac7abe0ba9
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
043ed2e22a
commit
6a479220b5
|
|
@ -41,10 +41,8 @@ body: |
|
|||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %1, %2
|
||||
|
||||
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
|
@ -70,10 +68,8 @@ body: |
|
|||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %1, %2
|
||||
|
||||
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
|
@ -96,11 +92,9 @@ body: |
|
|||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_HH_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %0, %2
|
||||
%4:sgpr(s32) = G_LSHR %1, %2
|
||||
|
||||
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||||
S_ENDPGM 0, implicit %5
|
||||
...
|
||||
|
|
@ -145,9 +139,7 @@ body: |
|
|||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_MOV_B32_]], [[COPY]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
|
||||
%1:sgpr(s32) = G_CONSTANT i32 0
|
||||
|
||||
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
|
@ -167,9 +159,7 @@ body: |
|
|||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: S_ENDPGM 0, implicit [[COPY]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
|
||||
%1:sgpr(s32) = G_IMPLICIT_DEF
|
||||
|
||||
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
|
@ -191,9 +181,7 @@ body: |
|
|||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[DEF]], [[COPY]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
|
||||
%1:sgpr(s32) = G_IMPLICIT_DEF
|
||||
|
||||
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %1, %0
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
|
@ -301,10 +289,144 @@ body: |
|
|||
; GFX9: S_ENDPGM 0, implicit [[S_LSHR_B32_]]
|
||||
%0:sgpr(s32) = G_CONSTANT i32 0
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %1, %2
|
||||
|
||||
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %0
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
# Don't use pack since it would duplicate the shift use
|
||||
---
|
||||
name: test_build_vector_trunc_s_pack_lh_multi_use
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_multi_use
|
||||
; GFX9: liveins: $sgpr0, $sgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||||
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %1, %2
|
||||
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
|
||||
S_ENDPGM 0, implicit %4, implicit %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_lhs
|
||||
; GFX9: liveins: $sgpr0, $sgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||||
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_PACK_LH_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LH_B32_B16 [[S_LSHR_B32_]], [[COPY1]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LH_B32_B16_]], implicit [[S_LSHR_B32_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %0, %2
|
||||
%4:sgpr(s32) = G_LSHR %1, %2
|
||||
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||||
S_ENDPGM 0, implicit %5, implicit %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_multi_use_rhs
|
||||
; GFX9: liveins: $sgpr0, $sgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
|
||||
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]], implicit [[S_LSHR_B32_1]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = G_CONSTANT i32 16
|
||||
%3:sgpr(s32) = G_LSHR %0, %2
|
||||
%4:sgpr(s32) = G_LSHR %1, %2
|
||||
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||||
S_ENDPGM 0, implicit %5, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_lh_wrong_shift_amt
|
||||
; GFX9: liveins: $sgpr0, $sgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
|
||||
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[COPY]], [[S_LSHR_B32_]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = G_CONSTANT i32 15
|
||||
%3:sgpr(s32) = G_LSHR %1, %2
|
||||
%4:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %0, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $sgpr0, $sgpr1
|
||||
|
||||
; GFX9-LABEL: name: test_build_vector_trunc_s_pack_hh_wrong_shift_amt
|
||||
; GFX9: liveins: $sgpr0, $sgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
|
||||
; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 15
|
||||
; GFX9: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX9: [[S_PACK_LL_B32_B16_:%[0-9]+]]:sreg_32 = S_PACK_LL_B32_B16 [[S_LSHR_B32_]], [[S_LSHR_B32_1]]
|
||||
; GFX9: S_ENDPGM 0, implicit [[S_PACK_LL_B32_B16_]]
|
||||
%0:sgpr(s32) = COPY $sgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr1
|
||||
%2:sgpr(s32) = G_CONSTANT i32 15
|
||||
%3:sgpr(s32) = G_LSHR %0, %2
|
||||
%4:sgpr(s32) = G_LSHR %1, %2
|
||||
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %3, %4
|
||||
S_ENDPGM 0, implicit %5
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue