maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

ARM: Handle physreg targets in RegPair hints gracefully 

Register coalescing can change the target of a RegPair hint to a
physreg, we should not crash on this. This also slightly improved the
way ARMBaseRegisterInfo::updateRegAllocHint() works.

llvm-svn: 233987
This commit is contained in:
Matthias Braun 2015-04-03 00:18:38 +00:00
parent 5d8c1e3f61
commit 6a42d7fd6b
2 changed files with 37 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -245,11 +245,15 @@ ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
// This register should preferably be even (Odd == 0) or odd (Odd == 1).
// Check if the other part of the pair has already been assigned, and provide
// the paired register as the first hint.
unsigned Paired = Hint.second;
if (Paired == 0)
return;
unsigned PairedPhys = 0;
if (VRM && VRM->hasPhys(Hint.second)) {
PairedPhys = getPairedGPR(VRM->getPhys(Hint.second), Odd, this);
if (PairedPhys && MRI.isReserved(PairedPhys))
PairedPhys = 0;
if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
PairedPhys = Paired;
} else if (VRM && VRM->hasPhys(Paired)) {
PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
}
// First prefer the paired physreg.
@ -284,9 +288,14 @@ ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
// change.
unsigned OtherReg = Hint.second;
Hint = MRI->getRegAllocationHint(OtherReg);
if (Hint.second == Reg)
// Make sure the pair has not already divorced.
// Make sure the pair has not already divorced.
if (Hint.second == Reg) {
MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
if (TargetRegisterInfo::isVirtualRegister(NewReg))
MRI->setRegAllocationHint(NewReg,
Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
: ARMRI::RegPairOdd, OtherReg);
}
}
}

22
llvm/test/CodeGen/ARM/regpair_hint_phys.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc -o - %s
; ARM target used to fail an assertion if RegPair{Odd|Even} hint pointed to a
; physreg.
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-apple-tvos8.3.0"
declare i8* @llvm.frameaddress(i32) #1
declare i8* @llvm.returnaddress(i32) #1
@somevar = global [2 x i32] [i32 0, i32 0]
define void @__ubsan_handle_shift_out_of_bounds() #0 {
entry:
%0 = tail call i8* @llvm.frameaddress(i32 0)
%1 = ptrtoint i8* %0 to i32
%2 = tail call i8* @llvm.returnaddress(i32 0)
%3 = ptrtoint i8* %2 to i32
%val0 = insertvalue [2 x i32] [i32 undef, i32 undef], i32 %3, 0
%val1 = insertvalue [2 x i32] %val0, i32 %1, 1
store [2 x i32] %val1, [2 x i32]* @somevar, align 8
ret void
}