forked from OSchip/llvm-project
[LLD][ELF][AVR] Implement the missing relocation types
Implements the missing relocation types for AVR target. The results have been cross-checked with binutils. Original patch by LemonBoy. Some changes by me. Differential Revision: https://reviews.llvm.org/D78741
This commit is contained in:
Ayke van Laethem
parent
d589372704
commit
69e60c9dc7
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@ -54,11 +54,131 @@ AVR::AVR() { noneRel = R_AVR_NONE; }
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RelExpr AVR::getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const {
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return R_ABS;
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switch (type) {
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case R_AVR_7_PCREL:
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case R_AVR_13_PCREL:
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return R_PC;
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default:
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return R_ABS;
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}
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}
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static void writeLDI(uint8_t *loc, uint64_t val) {
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write16le(loc, (read16le(loc) & 0xf0f0) | (val & 0xf0) << 4 | (val & 0x0f));
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}
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void AVR::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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switch (rel.type) {
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case R_AVR_8:
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checkUInt(loc, val, 8, rel);
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*loc = val;
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break;
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case R_AVR_16:
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// Note: this relocation is often used between code and data space, which
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// are 0x800000 apart in the output ELF file. The bitmask cuts off the high
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// bit.
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write16le(loc, val & 0xffff);
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break;
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case R_AVR_16_PM:
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checkAlignment(loc, val, 2, rel);
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checkUInt(loc, val >> 1, 16, rel);
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write16le(loc, val >> 1);
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break;
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case R_AVR_32:
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checkUInt(loc, val, 32, rel);
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write32le(loc, val);
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break;
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case R_AVR_LDI:
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checkUInt(loc, val, 8, rel);
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writeLDI(loc, val & 0xff);
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break;
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case R_AVR_LO8_LDI_NEG:
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writeLDI(loc, -val & 0xff);
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break;
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case R_AVR_LO8_LDI:
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writeLDI(loc, val & 0xff);
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break;
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case R_AVR_HI8_LDI_NEG:
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writeLDI(loc, (-val >> 8) & 0xff);
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break;
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case R_AVR_HI8_LDI:
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writeLDI(loc, (val >> 8) & 0xff);
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break;
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case R_AVR_HH8_LDI_NEG:
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writeLDI(loc, (-val >> 16) & 0xff);
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break;
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case R_AVR_HH8_LDI:
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writeLDI(loc, (val >> 16) & 0xff);
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break;
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case R_AVR_MS8_LDI_NEG:
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writeLDI(loc, (-val >> 24) & 0xff);
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break;
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case R_AVR_MS8_LDI:
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writeLDI(loc, (val >> 24) & 0xff);
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break;
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case R_AVR_LO8_LDI_PM:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (val >> 1) & 0xff);
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break;
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case R_AVR_HI8_LDI_PM:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (val >> 9) & 0xff);
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break;
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case R_AVR_HH8_LDI_PM:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (val >> 17) & 0xff);
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break;
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case R_AVR_LO8_LDI_PM_NEG:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (-val >> 1) & 0xff);
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break;
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case R_AVR_HI8_LDI_PM_NEG:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (-val >> 9) & 0xff);
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break;
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case R_AVR_HH8_LDI_PM_NEG:
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checkAlignment(loc, val, 2, rel);
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writeLDI(loc, (-val >> 17) & 0xff);
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break;
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case R_AVR_PORT5:
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checkUInt(loc, val, 5, rel);
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write16le(loc, (read16le(loc) & 0xff07) | (val << 3));
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break;
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case R_AVR_PORT6:
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checkUInt(loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xf9f0) | (val & 0x30) << 5 | (val & 0x0f));
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break;
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// Since every jump destination is word aligned we gain an extra bit
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case R_AVR_7_PCREL: {
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checkInt(loc, val, 7, rel);
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checkAlignment(loc, val, 2, rel);
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const uint16_t target = (val - 2) >> 1;
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write16le(loc, (read16le(loc) & 0xfc07) | ((target & 0x7f) << 3));
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break;
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}
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case R_AVR_13_PCREL: {
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checkAlignment(loc, val, 2, rel);
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const uint16_t target = (val - 2) >> 1;
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write16le(loc, (read16le(loc) & 0xf000) | (target & 0xfff));
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break;
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}
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case R_AVR_6:
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checkInt(loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xd3f8) | (val & 0x20) << 8 |
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(val & 0x18) << 7 | (val & 0x07));
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break;
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case R_AVR_6_ADIW:
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checkInt(loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xff30) | (val & 0x30) << 2 | (val & 0x0F));
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break;
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case R_AVR_CALL: {
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uint16_t hi = val >> 17;
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uint16_t lo = val >> 1;
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@ -0,0 +1,84 @@
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; REQUIRES: avr
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; RUN: llvm-mc -filetype=obj -triple=avr -mcpu=atmega328p %s -o %t.o
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; RUN: ld.lld %t.o --defsym=a=0x12345678 --defsym=b=30 -o %t
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; RUN: llvm-objdump -d --print-imm-hex %t | FileCheck %s
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; RUN: llvm-objdump -s %t | FileCheck --check-prefix=HEX %s
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.section .LDI,"ax",@progbits
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; CHECK-LABEL: section .LDI:
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; CHECK: ldi r20, 0x78
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; CHECK-NEXT: ldi r20, 0x56
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; CHECK-NEXT: ldi r20, 0x34
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; CHECK-NEXT: ldi r20, 0x12
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; CHECK-NEXT: ldi r20, 0x3c
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; CHECK-NEXT: ldi r20, 0x2b
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; CHECK-NEXT: ldi r20, 0x1a
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; CHECK-NEXT: ldi r20, 0xff
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ldi r20, lo8(a) ; R_AVR_LO8_LDI
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ldi r20, hi8(a) ; R_AVR_HI8_LDI
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ldi r20, hh8(a) ; R_AVR_HH8_LDI
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ldi r20, hhi8(a) ; R_AVR_MS8_LDI
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ldi r20, pm_lo8(a) ; R_AVR_LO8_LDI_PM
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ldi r20, pm_hi8(a) ; R_AVR_HI8_LDI_PM
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ldi r20, pm_hh8(a) ; R_AVR_HH8_LDI_PM
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ldi r20, b+225
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.section .LDI_NEG,"ax",@progbits
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; CHECK-LABEL: section .LDI_NEG:
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; CHECK: ldi r20, 0x88
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; CHECK-NEXT: ldi r20, 0xa9
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; CHECK-NEXT: ldi r20, 0xcb
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; CHECK-NEXT: ldi r20, 0xed
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; CHECK-NEXT: ldi r20, 0xc4
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; CHECK-NEXT: ldi r20, 0xd4
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; CHECK-NEXT: ldi r20, 0xe5
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ldi r20, lo8(-(a)) ; R_AVR_LO8_LDI_NEG
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ldi r20, hi8(-(a)) ; R_AVR_HI8_LDI_NEG
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ldi r20, hh8(-(a)) ; R_AVR_HH8_LDI_NEG
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ldi r20, hhi8(-(a)) ; R_AVR_MS8_LDI_NEG
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ldi r20, pm_lo8(-(a)) ; R_AVR_LO8_LDI_PM_NEG
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ldi r20, pm_hi8(-(a)) ; R_AVR_HI8_LDI_PM_NEG
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ldi r20, pm_hh8(-(a)) ; R_AVR_HH8_LDI_PM_NEG
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;; The disassembler is not yet able to decode those opcodes
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;; 9e 8e std Y+30, r9
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;; 9e 8c ldd r9, Y+30
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;; 4e 96 adiw r24, 0x1e
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.section .SIX,"ax",@progbits
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; HEX-LABEL: section .SIX:
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; HEX-NEXT: 9e8e9e8c 4e96
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std Y+b, r9 ; R_AVR_6
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ldd r9, Y+b ; R_AVR_6
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adiw r24, b ; R_AVR_6_ADIW
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.section .PORT,"ax",@progbits
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; CHECK-LABEL: section .PORT:
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; CHECK: in r20, 0x1e
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; CHECK-NEXT: sbic 0x1e, 0x1
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in r20, b ; R_AVR_PORT6
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sbic b, 1 ; R_AVR_PORT5
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;; The disassembler is not yet able to decode those opcodes
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;; 0f c0 rjmp .+30
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;; ee cf rjmp .-36
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;; 69 f0 breq .+26
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;; 61 f3 breq .-40
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.section .PCREL,"ax",@progbits
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; HEX-LABEL: section .PCREL:
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; HEX-NEXT: 0fc0eecf 69f061f3
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foo:
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rjmp foo + 32 ; R_AVR_13_PCREL
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rjmp foo - 32 ; R_AVR_13_PCREL
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breq foo + 32 ; R_AVR_7_PCREL
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breq foo - 32 ; R_AVR_7_PCREL
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.section .DATA,"ax",@progbits
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; HEX-LABEL: section .DATA:
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; HEX-NEXT: {{.*}} 1e1e000f 00785634 12
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.byte b ; R_AVR_8
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.short b ; R_AVR_16
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.short gs(b) ; R_AVR_16_PM
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.long a ; R_AVR_32
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