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Fix disassembly of some VST1 instructions. 

llvm-svn: 143507
This commit is contained in:
Owen Anderson 2011-11-01 22:18:13 +00:00
parent c3ae7c363e
commit 69e54a740c
2 changed files with 21 additions and 6 deletions
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24
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2240,13 +2240,27 @@ static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
// AddrMode6 Offset (register)
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
switch (Inst.getOpcode()) {
default:
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
break;
case ARM::VST1d8wb_fixed:
case ARM::VST1d16wb_fixed:
case ARM::VST1d32wb_fixed:
case ARM::VST1d64wb_fixed:
case ARM::VST1q8wb_fixed:
case ARM::VST1q16wb_fixed:
case ARM::VST1q32wb_fixed:
case ARM::VST1q64wb_fixed:
break;
}
// First input register
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;

3
llvm/test/MC/Disassembler/ARM/neon.txt
View File

@ -1861,4 +1861,5 @@
# CHECK: vld1.8 {d23, d24, d25}, [r6, :64]!
0x9d 0x62 0x6f 0xf4
# CHECK: vld1.32 {d22, d23, d24, d25}, [pc, :64]!
0x9d 0xaa 0x41 0xf4
# CHECK: vst1.32 {d26, d27}, [r1, :64]!