forked from OSchip/llvm-project
[sanitizer] Align & pad the allocator structures to the cacheline size
Summary: Both `SizeClassInfo` structures for the 32-bit primary & `RegionInfo` structures for the 64-bit primary can be used by different threads, and as such they should be aligned & padded to the cacheline size to avoid false sharing. The former was padded but the array was not aligned, the latter was not padded but we lucked up as the size of the structure was 192 bytes, and aligned by the properties of `mmap`. I plan on adding a couple of fields to the `RegionInfo`, and some highly threaded tests pointed out that without proper padding & alignment, performance was getting a hit - and it is going away with proper padding. This patch makes sure that we are properly padded & aligned for both. I used a template to avoid padding if the size is already a multiple of the cacheline size. There might be a better way to do this, I am open to suggestions. Reviewers: alekseyshl, dvyukov Reviewed By: alekseyshl Subscribers: kubamracek, delcypher, #sanitizers, llvm-commits Differential Revision: https://reviews.llvm.org/D44261 llvm-svn: 327145
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@ -266,14 +266,12 @@ class SizeClassAllocator32 {
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static const uptr kRegionSize = 1 << kRegionSizeLog;
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static const uptr kNumPossibleRegions = kSpaceSize / kRegionSize;
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struct SizeClassInfo {
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struct ALIGNED(kCacheLineSize) SizeClassInfo {
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SpinMutex mutex;
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IntrusiveList<TransferBatch> free_list;
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u32 rand_state;
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char padding[kCacheLineSize - 2 * sizeof(uptr) -
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sizeof(IntrusiveList<TransferBatch>)];
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};
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COMPILER_CHECK(sizeof(SizeClassInfo) == kCacheLineSize);
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COMPILER_CHECK(sizeof(SizeClassInfo) % kCacheLineSize == 0);
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uptr ComputeRegionId(uptr mem) {
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const uptr res = mem >> kRegionSizeLog;
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@ -299,7 +297,7 @@ class SizeClassAllocator32 {
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}
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SizeClassInfo *GetSizeClassInfo(uptr class_id) {
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CHECK_LT(class_id, kNumClasses);
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DCHECK_LT(class_id, kNumClasses);
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return &size_class_info_array[class_id];
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}
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@ -80,6 +80,8 @@ class SizeClassAllocator64 {
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}
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SetReleaseToOSIntervalMs(release_to_os_interval_ms);
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MapWithCallbackOrDie(SpaceEnd(), AdditionalSize());
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// Check that the RegionInfo array is aligned on the CacheLine size.
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DCHECK_EQ(SpaceEnd() & (kCacheLineSize - 1), 0);
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}
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s32 ReleaseToOSIntervalMs() const {
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@ -302,7 +304,7 @@ class SizeClassAllocator64 {
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static uptr AdditionalSize() {
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return RoundUpTo(sizeof(RegionInfo) * kNumClassesRounded,
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GetPageSizeCached());
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GetPageSizeCached());
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}
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typedef SizeClassMap SizeClassMapT;
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@ -584,7 +586,7 @@ class SizeClassAllocator64 {
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u64 last_released_bytes;
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};
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struct RegionInfo {
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struct ALIGNED(kCacheLineSize) RegionInfo {
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BlockingMutex mutex;
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uptr num_freed_chunks; // Number of elements in the freearray.
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uptr mapped_free_array; // Bytes mapped for freearray.
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@ -597,12 +599,11 @@ class SizeClassAllocator64 {
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Stats stats;
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ReleaseToOsInfo rtoi;
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};
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COMPILER_CHECK(sizeof(RegionInfo) >= kCacheLineSize);
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COMPILER_CHECK(sizeof(RegionInfo) % kCacheLineSize == 0);
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RegionInfo *GetRegionInfo(uptr class_id) const {
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CHECK_LT(class_id, kNumClasses);
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RegionInfo *regions =
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reinterpret_cast<RegionInfo *>(SpaceBeg() + kSpaceSize);
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DCHECK_LT(class_id, kNumClasses);
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RegionInfo *regions = reinterpret_cast<RegionInfo *>(SpaceEnd());
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return ®ions[class_id];
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}
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@ -40,10 +40,12 @@ const uptr kWordSize = SANITIZER_WORDSIZE / 8;
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const uptr kWordSizeInBits = 8 * kWordSize;
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#if defined(__powerpc__) || defined(__powerpc64__)
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const uptr kCacheLineSize = 128;
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constexpr uptr kCacheLineSize = 128;
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#else
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const uptr kCacheLineSize = 64;
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constexpr uptr kCacheLineSize = 64;
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#endif
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// Check that the CacheLine size is a power-of-two.
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COMPILER_CHECK((kCacheLineSize & (kCacheLineSize - 1)) == 0);
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const uptr kMaxPathLength = 4096;
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