forked from OSchip/llvm-project
AMDGPU/GlobalISel: Legalize llvm.amdgcn.s.buffer.load
The 96-bit results need to be widened. I find the interaction between LegalizerHelper and MIRBuilder somewhat awkward. The custom legalization is called by the LegalizerHelper, but then does not have access to the helper. You have to construct a new helper, which then does not own the MachineIRBuilder, but does modify it. Maybe custom legalization should be passed the helper?
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
748bb5a0f1
commit
69cc9f3046
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@ -42,6 +42,20 @@ using namespace LegalizeMutations;
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using namespace LegalityPredicates;
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using namespace MIPatternMatch;
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// Round the number of elements to the next power of two elements
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static LLT getPow2VectorType(LLT Ty) {
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unsigned NElts = Ty.getNumElements();
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unsigned Pow2NElts = 1 << Log2_32_Ceil(NElts);
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return Ty.changeNumElements(Pow2NElts);
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}
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// Round the number of bits to the next power of two bits
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static LLT getPow2ScalarType(LLT Ty) {
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unsigned Bits = Ty.getSizeInBits();
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unsigned Pow2Bits = 1 << Log2_32_Ceil(Bits);
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return LLT::scalar(Pow2Bits);
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}
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static LegalityPredicate isMultiple32(unsigned TypeIdx,
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unsigned MaxSize = 1024) {
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return [=](const LegalityQuery &Query) {
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@ -2959,6 +2973,33 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeSBufferLoad(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const {
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Register Dst = MI.getOperand(0).getReg();
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LLT Ty = B.getMRI()->getType(Dst);
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unsigned Size = Ty.getSizeInBits();
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// There are no 96-bit result scalar loads, but widening to 128-bit should
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// always be legal. We may need to restore this to a 96-bit result if it turns
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// out this needs to be converted to a vector load during RegBankSelect.
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if (isPowerOf2_32(Size))
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return true;
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LegalizerHelper Helper(B.getMF(), *this, Observer, B);
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B.setInstr(MI);
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Observer.changingInstr(MI);
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if (Ty.isVector())
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Helper.moreElementsVectorDst(MI, getPow2VectorType(Ty), 0);
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else
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Helper.widenScalarDst(MI, getPow2ScalarType(Ty), 0);
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Observer.changedInstr(MI);
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return true;
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}
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bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const {
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@ -3075,6 +3116,8 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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MI.eraseFromParent();
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return true;
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}
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case Intrinsic::amdgcn_s_buffer_load:
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return legalizeSBufferLoad(MI, B, Observer);
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case Intrinsic::amdgcn_raw_buffer_store:
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case Intrinsic::amdgcn_struct_buffer_store:
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return legalizeBufferStore(MI, MRI, B, false, false);
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@ -138,6 +138,10 @@ public:
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GISelChangeObserver &Observer,
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const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
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bool legalizeSBufferLoad(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const;
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bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
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bool IsInc) const;
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@ -0,0 +1,136 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=legalizer %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: s_buffer_load_v3s32
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v3s32
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_v3p3
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v3p3
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<4 x p3>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x p3>) = G_EXTRACT [[INT]](<4 x p3>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x p3>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<3 x p3>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_v6s16
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v6s16
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s16>) = G_EXTRACT [[INT]](<8 x s16>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s16>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<6 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_v6s32
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v6s32
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<8 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<6 x s32>) = G_EXTRACT [[INT]](<8 x s32>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<6 x s32>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<6 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_v3s64
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v3s64
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s64>) = G_EXTRACT [[INT]](<4 x s64>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s64>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<3 x s64>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_v12s8
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_v12s8
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<12 x s8>) = G_EXTRACT [[INT]](<16 x s8>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<12 x s8>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<12 x s8>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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---
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name: s_buffer_load_s96
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN-LABEL: name: s_buffer_load_s96
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; GCN: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: [[INT:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), [[COPY]](<4 x s32>), [[C]](s32), 0
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; GCN: [[EXTRACT:%[0-9]+]]:_(<3 x s32>) = G_EXTRACT [[INT]](<4 x s32>), 0
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; GCN: S_ENDPGM 0, implicit [[EXTRACT]](<3 x s32>)
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%0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
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%1:_(s32) = G_CONSTANT i32 0
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%2:_(<3 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.buffer.load), %0, %1, 0
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S_ENDPGM 0, implicit %2
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...
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