From 69c6008e493566df7115784d9ed0f382fd979825 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 20 May 2015 14:18:59 +0000 Subject: [PATCH] Revert r237789 - [mips] The naming convention for private labels is ABI dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792 --- llvm/include/llvm/MC/MCAsmInfo.h | 6 -- llvm/lib/CodeGen/LLVMTargetMachine.cpp | 1 - .../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 3 - .../Target/Mips/MCTargetDesc/MipsABIInfo.h | 2 - .../Mips/MCTargetDesc/MipsMCAsmInfo.cpp | 15 +-- .../Target/Mips/MCTargetDesc/MipsMCAsmInfo.h | 4 - llvm/lib/Target/Mips/MipsTargetMachine.cpp | 1 - llvm/test/CodeGen/Mips/analyzebranch.ll | 8 +- llvm/test/CodeGen/Mips/atomic.ll | 84 ++++++++--------- llvm/test/CodeGen/Mips/blez_bgez.ll | 4 +- llvm/test/CodeGen/Mips/blockaddr.ll | 48 +++++----- llvm/test/CodeGen/Mips/fpbr.ll | 24 ++--- llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 16 ++-- llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll | 4 +- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 8 +- llvm/test/CodeGen/Mips/llvm-ir/select.ll | 92 +++++++++---------- llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 16 ++-- llvm/test/CodeGen/Mips/longbranch.ll | 60 ++++++------ llvm/test/CodeGen/Mips/octeon.ll | 16 ++-- llvm/test/CodeGen/Mips/private_label.ll | 11 --- 20 files changed, 192 insertions(+), 231 deletions(-) delete mode 100644 llvm/test/CodeGen/Mips/private_label.ll diff --git a/llvm/include/llvm/MC/MCAsmInfo.h b/llvm/include/llvm/MC/MCAsmInfo.h index 3dd27934c144..64dc8abd6382 100644 --- a/llvm/include/llvm/MC/MCAsmInfo.h +++ b/llvm/include/llvm/MC/MCAsmInfo.h @@ -27,7 +27,6 @@ class MCSection; class MCStreamer; class MCSymbol; class MCContext; -class LLVMTargetMachine; namespace WinEH { enum class EncodingType { @@ -546,11 +545,6 @@ public: } bool shouldUseLogicalShr() const { return UseLogicalShr; } - - /// Finish initialization of this object. Few targets will need to use this - /// but it's useful when the assembly syntax is ABI dependant as is the case - /// for Mips. - virtual void finishInit(const LLVMTargetMachine &) {} }; } diff --git a/llvm/lib/CodeGen/LLVMTargetMachine.cpp b/llvm/lib/CodeGen/LLVMTargetMachine.cpp index d49c4f0be5c1..610c9f47bac7 100644 --- a/llvm/lib/CodeGen/LLVMTargetMachine.cpp +++ b/llvm/lib/CodeGen/LLVMTargetMachine.cpp @@ -67,7 +67,6 @@ void LLVMTargetMachine::initAsmInfo() { if (Options.CompressDebugSections) TmpAsmInfo->setCompressDebugSections(true); - TmpAsmInfo->finishInit(*this); AsmInfo = TmpAsmInfo; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index d2b010486b5a..b1f7c2f22594 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -122,6 +122,3 @@ unsigned MipsABIInfo::GetEhDataReg(unsigned I) const { return IsN64() ? EhDataReg64[I] : EhDataReg[I]; } -const char *MipsABIInfo::GetPrivateLabelPrefix() const { - return IsO32() ? "$" : ".L"; -} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index 1e9d57b82b9b..9a6ba9467659 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -71,8 +71,6 @@ public: inline bool ArePtrs64bit() const { return IsN64(); } unsigned GetEhDataReg(unsigned I) const; - - const char *GetPrivateLabelPrefix() const; }; } diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index b47ca0b5cb5f..e2bd5a815ab1 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -12,10 +12,7 @@ //===----------------------------------------------------------------------===// #include "MipsMCAsmInfo.h" -#include "MCTargetDesc/MipsABIInfo.h" -#include "MipsTargetMachine.h" #include "llvm/ADT/Triple.h" -#include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -32,14 +29,12 @@ MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) { PointerSize = CalleeSaveStackSlotSize = 8; } - // These two are overridden in finishInit() - PrivateGlobalPrefix = "$"; - PrivateLabelPrefix = "$"; - AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Data32bitsDirective = "\t.4byte\t"; Data64bitsDirective = "\t.8byte\t"; + PrivateGlobalPrefix = "$"; + PrivateLabelPrefix = "$"; CommentString = "#"; ZeroDirective = "\t.space\t"; GPRel32Directive = "\t.gpword\t"; @@ -49,9 +44,3 @@ MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) { ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; } - -void MipsMCAsmInfo::finishInit(const LLVMTargetMachine &TM) { - const MipsABIInfo &ABI = static_cast(TM).getABI(); - PrivateGlobalPrefix = ABI.GetPrivateLabelPrefix(); - PrivateLabelPrefix = ABI.GetPrivateLabelPrefix(); -} diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h index aed702320d73..59ff1c41ed6e 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -18,15 +18,11 @@ namespace llvm { class StringRef; - class MipsABIInfo; - class LLVMTargetMachine; class MipsMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: explicit MipsMCAsmInfo(StringRef TT); - - void finishInit(const LLVMTargetMachine &TM) override; }; } // namespace llvm diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 6036247f2ee6..b279184ea304 100644 --- a/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -24,7 +24,6 @@ #include "MipsSEISelLowering.h" #include "MipsSEInstrInfo.h" #include "MipsTargetObjectFile.h" -#include "MCTargetDesc/MipsMCAsmInfo.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/IR/LegacyPassManager.h" diff --git a/llvm/test/CodeGen/Mips/analyzebranch.ll b/llvm/test/CodeGen/Mips/analyzebranch.ll index 4f17891f2473..d5ecaaeddc33 100644 --- a/llvm/test/CodeGen/Mips/analyzebranch.ll +++ b/llvm/test/CodeGen/Mips/analyzebranch.ll @@ -10,7 +10,7 @@ define double @foo(double %a, double %b) nounwind readnone { entry: ; ALL-LABEL: foo: -; FCC: bc1f {{(\$|.L)BB}} +; FCC: bc1f $BB ; FCC: nop ; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]] @@ -19,7 +19,7 @@ entry: ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], {{(\$|.L)BB}} +; GPR: bnez $[[GPRCC]], $BB %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -43,14 +43,14 @@ define void @f1(float %f) nounwind { entry: ; ALL-LABEL: f1: -; FCC: bc1f {{(\$|.L)BB}} +; FCC: bc1f $BB ; FCC: nop ; GPR: mtc1 $zero, $[[Z:f[0-9]]] ; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], {{(\$|.L)BB}} +; GPR: beqz $[[GPRCC]], $BB %cmp = fcmp une float %f, 0.000000e+00 br i1 %cmp, label %if.then, label %if.end diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll index 96d9150b1761..031cce0b6074 100644 --- a/llvm/test/CodeGen/Mips/atomic.ll +++ b/llvm/test/CodeGen/Mips/atomic.ll @@ -23,12 +23,12 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: sc $[[R2]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] -; MICROMIPS: beqzc $[[R2]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { @@ -41,13 +41,13 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 ; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]] ; ALL: sc $[[R2]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] -; MICROMIPS: beqzc $[[R2]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicSwap32(i32 signext %newval) nounwind { @@ -63,11 +63,11 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x) -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll ${{[0-9]+}}, 0($[[R0]]) ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] -; MICROMIPS: beqzc $[[R2]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { @@ -84,13 +84,13 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $2, 0($[[R0]]) -; ALL: bne $2, $4, [[BB1:(\$|.L)[A-Z_0-9]+]] +; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] -; MICROMIPS: beqzc $[[R2]], [[BB0]] -; ALL: [[BB1]]: +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; ALL: $[[BB1]]: } @@ -118,15 +118,15 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] -; MICROMIPS: beqzc $[[R14]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -158,15 +158,15 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] -; MICROMIPS: beqzc $[[R14]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -198,7 +198,7 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] ; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]] @@ -206,8 +206,8 @@ entry: ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] -; MICROMIPS: beqzc $[[R14]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -239,14 +239,14 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] -; MICROMIPS: beqzc $[[R14]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -283,18 +283,18 @@ entry: ; ALL: andi $[[R11:[0-9]+]], $5, 255 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]] +; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] -; MICROMIPS: beqzc $[[R16]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; ALL: [[BB1]]: +; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 @@ -324,18 +324,18 @@ entry: ; ALL: andi $[[R11:[0-9]+]], $6, 255 ; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]] +; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R16]], [[BB0]] -; MICROMIPS: beqzc $[[R16]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] -; ALL: [[BB1]]: +; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 @@ -371,15 +371,15 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) ; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] ; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] ; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] ; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] ; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], [[BB0]] -; MICROMIPS: beqzc $[[R14]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] +; MICROMIPS: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -438,10 +438,10 @@ entry: ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( ; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024 -; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]: +; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]]) ; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 ; ALL: sc $[[R2]], 0($[[PTR]]) -; NOT-MICROMIPS: beqz $[[R2]], [[BB0]] -; MICROMIPS: beqzc $[[R2]], [[BB0]] +; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] +; MICROMIPS: beqzc $[[R2]], $[[BB0]] } diff --git a/llvm/test/CodeGen/Mips/blez_bgez.ll b/llvm/test/CodeGen/Mips/blez_bgez.ll index 8ff399962748..dcda047f8d09 100644 --- a/llvm/test/CodeGen/Mips/blez_bgez.ll +++ b/llvm/test/CodeGen/Mips/blez_bgez.ll @@ -2,7 +2,7 @@ ; RUN: llc -march=mips64el < %s | FileCheck %s ; CHECK-LABEL: test_blez: -; CHECK: blez ${{[0-9]+}}, {{(\$|.L)BB}} +; CHECK: blez ${{[0-9]+}}, $BB define void @test_blez(i32 %a) { entry: @@ -20,7 +20,7 @@ if.end: declare void @foo1() ; CHECK-LABEL: test_bgez: -; CHECK: bgez ${{[0-9]+}}, {{(\$|.L)BB}} +; CHECK: bgez ${{[0-9]+}}, $BB define void @test_bgez(i32 %a) { entry: diff --git a/llvm/test/CodeGen/Mips/blockaddr.ll b/llvm/test/CodeGen/Mips/blockaddr.ll index aafdca5cf4bc..f74363702af5 100644 --- a/llvm/test/CodeGen/Mips/blockaddr.ll +++ b/llvm/test/CodeGen/Mips/blockaddr.ll @@ -14,30 +14,30 @@ entry: ret i8* %x } -; PIC-O32: lw $[[R0:[0-9]+]], %got([[T0:(\$|.L)tmp[0-9]+]]) -; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo([[T0]]) -; PIC-O32: lw $[[R1:[0-9]+]], %got([[T1:(\$|.L)tmp[0-9]+]]) -; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo([[T1]]) -; STATIC-O32: lui $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]]) -; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]]) -; STATIC-O32: lui $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]]) -; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]]) -; PIC-N32: lw $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]]) -; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]]) -; PIC-N32: lw $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]]) -; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]]) -; STATIC-N32: lui $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]]) -; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]]) -; STATIC-N32: lui $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]]) -; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]]) -; PIC-N64: ld $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]]) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]]) -; PIC-N64: ld $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]]) -; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]]) -; STATIC-N64: ld $[[R2:[0-9]+]], %got_page([[T2:(\$|.L)tmp[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst([[T2]]) -; STATIC-N64: ld $[[R3:[0-9]+]], %got_page([[T3:(\$|.L)tmp[0-9]+]]) -; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst([[T3]]) +; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]]) +; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]]) +; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]]) +; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]]) +; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) +; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) +; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) +; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) +; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) +; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) +; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]]) +; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]]) +; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]]) +; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]]) +; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]]) +; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]]) +; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]]) +; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]]) +; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]]) ; STATIC-MIPS16-1: .ent f ; STATIC-MIPS16-2: .ent f ; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]]) diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll index 1b899f31328a..27d7094376e6 100644 --- a/llvm/test/CodeGen/Mips/fpbr.ll +++ b/llvm/test/CodeGen/Mips/fpbr.ll @@ -11,14 +11,14 @@ entry: ; 32-FCC: c.eq.s $f12, $f14 ; 64-FCC: c.eq.s $f12, $f13 -; FCC: bc1f {{(\$|.L)BB0_2}} +; FCC: bc1f $BB0_2 ; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], {{(\$|.L)BB0_2}} +; GPR: bnez $[[GPRCC]], $BB0_2 %cmp = fcmp oeq float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -45,13 +45,13 @@ entry: ; 32-FCC: c.olt.s $f12, $f14 ; 64-FCC: c.olt.s $f12, $f13 -; FCC: bc1f {{(\$|.L)BB1_2}} +; FCC: bc1f $BB1_2 ; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], {{(\$|.L)BB1_2}} +; GPR: bnez $[[GPRCC]], $BB1_2 %cmp = fcmp olt float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -74,13 +74,13 @@ entry: ; 32-FCC: c.ole.s $f12, $f14 ; 64-FCC: c.ole.s $f12, $f13 -; FCC: bc1t {{(\$|.L)BB2_2}} +; FCC: bc1t $BB2_2 ; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], {{(\$|.L)BB2_2}} +; GPR: beqz $[[GPRCC]], $BB2_2 %cmp = fcmp ugt float %f2, %f3 br i1 %cmp, label %if.else, label %if.then @@ -103,14 +103,14 @@ entry: ; 32-FCC: c.eq.d $f12, $f14 ; 64-FCC: c.eq.d $f12, $f13 -; FCC: bc1f {{(\$|.L)BB3_2}} +; FCC: bc1f $BB3_2 ; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], {{(\$|.L)BB3_2}} +; GPR: bnez $[[GPRCC]], $BB3_2 %cmp = fcmp oeq double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -133,13 +133,13 @@ entry: ; 32-FCC: c.olt.d $f12, $f14 ; 64-FCC: c.olt.d $f12, $f13 -; FCC: bc1f {{(\$|.L)BB4_2}} +; FCC: bc1f $BB4_2 ; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], {{(\$|.L)BB4_2}} +; GPR: bnez $[[GPRCC]], $BB4_2 %cmp = fcmp olt double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -162,13 +162,13 @@ entry: ; 32-FCC: c.ole.d $f12, $f14 ; 64-FCC: c.ole.d $f12, $f13 -; FCC: bc1t {{(\$|.L)BB5_2}} +; FCC: bc1t $BB5_2 ; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12 ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], {{(\$|.L)BB5_2}} +; GPR: beqz $[[GPRCC]], $BB5_2 %cmp = fcmp ugt double %f2, %f3 br i1 %cmp, label %if.else, label %if.then diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll index 6c6e7cd50768..cad4a39d7743 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -88,18 +88,18 @@ entry: ; M2: srav $[[T0:[0-9]+]], $4, $7 ; M2: andi $[[T1:[0-9]+]], $7, 32 - ; M2: bnez $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]] + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] ; M2: move $3, $[[T0]] ; M2: srlv $[[T2:[0-9]+]], $5, $7 ; M2: not $[[T3:[0-9]+]], $7 ; M2: sll $[[T4:[0-9]+]], $4, 1 ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] ; M2: or $3, $[[T3]], $[[T2]] - ; M2: [[BB0]]: - ; M2: beqz $[[T1]], [[BB1:(\$|.L)BB[0-9_]+]] + ; M2: $[[BB0]]: + ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] ; M2: nop ; M2: sra $2, $4, 31 - ; M2: [[BB1]]: + ; M2: $[[BB1]]: ; M2: jr $ra ; M2: nop @@ -146,18 +146,18 @@ entry: ; M3: sll $[[T0:[0-9]+]], $7, 0 ; M3: dsrav $[[T1:[0-9]+]], $4, $7 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64 - ; M3: bnez $[[T3:[0-9]+]], [[BB0:(\$|.L)BB[0-9_]+]] + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] ; M3: move $3, $[[T1]] ; M3: dsrlv $[[T4:[0-9]+]], $5, $7 ; M3: dsll $[[T5:[0-9]+]], $4, 1 ; M3: not $[[T6:[0-9]+]], $[[T0]] ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] ; M3: or $3, $[[T7]], $[[T4]] - ; M3: [[BB0]]: - ; M3: beqz $[[T3]], [[BB1:(\$|.L)BB[0-9_]+]] + ; M3: $[[BB0]]: + ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] ; M3: nop ; M3: dsra $2, $4, 63 - ; M3: [[BB1]]: + ; M3: $[[BB1]]: ; M3: jr $ra ; M3: nop diff --git a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll index 12dd62da207d..debfeb35b213 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -17,12 +17,12 @@ define i32 @br(i8 *%addr) { ; NOT-R6: jr $4 #