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Revert r237789 - [mips] The naming convention for private labels is ABI dependant. 

It works, but I've noticed that I missed several callers of createMCAsmInfo()
and many don't have a TargetMachine to provide.

llvm-svn: 237792
This commit is contained in:
Daniel Sanders 2015-05-20 14:18:59 +00:00
parent 56b12d75bf
commit 69c6008e49
20 changed files with 192 additions and 231 deletions
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6
llvm/include/llvm/MC/MCAsmInfo.h
View File

@ -27,7 +27,6 @@ class MCSection;
class MCStreamer;
class MCSymbol;
class MCContext;
class LLVMTargetMachine;
namespace WinEH {
enum class EncodingType {
@ -546,11 +545,6 @@ public:
}
bool shouldUseLogicalShr() const { return UseLogicalShr; }
/// Finish initialization of this object. Few targets will need to use this
/// but it's useful when the assembly syntax is ABI dependant as is the case
/// for Mips.
virtual void finishInit(const LLVMTargetMachine &) {}
};
}

1
llvm/lib/CodeGen/LLVMTargetMachine.cpp
View File

@ -67,7 +67,6 @@ void LLVMTargetMachine::initAsmInfo() {
if (Options.CompressDebugSections)
TmpAsmInfo->setCompressDebugSections(true);
TmpAsmInfo->finishInit(*this);
AsmInfo = TmpAsmInfo;
}

3
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
View File

@ -122,6 +122,3 @@ unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
return IsN64() ? EhDataReg64[I] : EhDataReg[I];
}
const char *MipsABIInfo::GetPrivateLabelPrefix() const {
return IsO32() ? "$" : ".L";
}

2
llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
View File

@ -71,8 +71,6 @@ public:
inline bool ArePtrs64bit() const { return IsN64(); }
unsigned GetEhDataReg(unsigned I) const;
const char *GetPrivateLabelPrefix() const;
};
}

15
llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp
View File

@ -12,10 +12,7 @@
//===----------------------------------------------------------------------===//
#include "MipsMCAsmInfo.h"
#include "MCTargetDesc/MipsABIInfo.h"
#include "MipsTargetMachine.h"
#include "llvm/ADT/Triple.h"
#include "llvm/Target/TargetMachine.h"
using namespace llvm;
@ -32,14 +29,12 @@ MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) {
PointerSize = CalleeSaveStackSlotSize = 8;
}
// These two are overridden in finishInit()
PrivateGlobalPrefix = "$";
PrivateLabelPrefix = "$";
AlignmentIsInBytes = false;
Data16bitsDirective = "\t.2byte\t";
Data32bitsDirective = "\t.4byte\t";
Data64bitsDirective = "\t.8byte\t";
PrivateGlobalPrefix = "$";
PrivateLabelPrefix = "$";
CommentString = "#";
ZeroDirective = "\t.space\t";
GPRel32Directive = "\t.gpword\t";
@ -49,9 +44,3 @@ MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) {
ExceptionsType = ExceptionHandling::DwarfCFI;
DwarfRegNumForCFI = true;
}
void MipsMCAsmInfo::finishInit(const LLVMTargetMachine &TM) {
const MipsABIInfo &ABI = static_cast<const MipsTargetMachine &>(TM).getABI();
PrivateGlobalPrefix = ABI.GetPrivateLabelPrefix();
PrivateLabelPrefix = ABI.GetPrivateLabelPrefix();
}

4
llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h
View File

@ -18,15 +18,11 @@
namespace llvm {
class StringRef;
class MipsABIInfo;
class LLVMTargetMachine;
class MipsMCAsmInfo : public MCAsmInfoELF {
void anchor() override;
public:
explicit MipsMCAsmInfo(StringRef TT);
void finishInit(const LLVMTargetMachine &TM) override;
};
} // namespace llvm

1
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -24,7 +24,6 @@
#include "MipsSEISelLowering.h"
#include "MipsSEInstrInfo.h"
#include "MipsTargetObjectFile.h"
#include "MCTargetDesc/MipsMCAsmInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/IR/LegacyPassManager.h"

8
llvm/test/CodeGen/Mips/analyzebranch.ll
View File

@ -10,7 +10,7 @@ define double @foo(double %a, double %b) nounwind readnone {
entry:
; ALL-LABEL: foo:
; FCC: bc1f {{(\$|.L)BB}}
; FCC: bc1f $BB
; FCC: nop
; 32-GPR: mtc1 $zero, $[[Z:f[0-9]]]
@ -19,7 +19,7 @@ entry:
; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], {{(\$|.L)BB}}
; GPR: bnez $[[GPRCC]], $BB
%cmp = fcmp ogt double %a, 0.000000e+00
br i1 %cmp, label %if.end6, label %if.else
@ -43,14 +43,14 @@ define void @f1(float %f) nounwind {
entry:
; ALL-LABEL: f1:
; FCC: bc1f {{(\$|.L)BB}}
; FCC: bc1f $BB
; FCC: nop
; GPR: mtc1 $zero, $[[Z:f[0-9]]]
; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]]
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: beqz $[[GPRCC]], {{(\$|.L)BB}}
; GPR: beqz $[[GPRCC]], $BB
%cmp = fcmp une float %f, 0.000000e+00
br i1 %cmp, label %if.then, label %if.end

84
llvm/test/CodeGen/Mips/atomic.ll
View File

@ -23,12 +23,12 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
; ALL: sc $[[R2]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
}
define i32 @AtomicLoadNand32(i32 signext %incr) nounwind {
@ -41,13 +41,13 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[R0]])
; ALL: and $[[R3:[0-9]+]], $[[R1]], $4
; ALL: nor $[[R2:[0-9]+]], $zero, $[[R3]]
; ALL: sc $[[R2]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
}
define i32 @AtomicSwap32(i32 signext %newval) nounwind {
@ -63,11 +63,11 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll ${{[0-9]+}}, 0($[[R0]])
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
}
define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
@ -84,13 +84,13 @@ entry:
; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x)
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $2, 0($[[R0]])
; ALL: bne $2, $4, [[BB1:(\$|.L)[A-Z_0-9]+]]
; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
; ALL: sc $[[R2:[0-9]+]], 0($[[R0]])
; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], [[BB0]]
; ALL: [[BB1]]:
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
; ALL: $[[BB1]]:
}
@ -118,15 +118,15 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@ -158,15 +158,15 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@ -198,7 +198,7 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]]
@ -206,8 +206,8 @@ entry:
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@ -239,14 +239,14 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: and $[[R18:[0-9]+]], $[[R9]], $[[R7]]
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@ -283,18 +283,18 @@ entry:
; ALL: andi $[[R11:[0-9]+]], $5, 255
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; ALL: bne $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]]
; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]]
; ALL: [[BB1]]:
; ALL: $[[BB1]]:
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
@ -324,18 +324,18 @@ entry:
; ALL: andi $[[R11:[0-9]+]], $6, 255
; ALL: sllv $[[R12:[0-9]+]], $[[R11]], $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R13:[0-9]+]], 0($[[R2]])
; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]]
; ALL: bne $[[R14]], $[[R10]], [[BB1:(\$|.L)[A-Z_0-9]+]]
; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]]
; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]]
; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]]
; ALL: sc $[[R16]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R16]], [[BB0]]
; MICROMIPS: beqzc $[[R16]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]]
; MICROMIPS: beqzc $[[R16]], $[[BB0]]
; ALL: [[BB1]]:
; ALL: $[[BB1]]:
; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]]
; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24
@ -371,15 +371,15 @@ entry:
; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]]
; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]]
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R10:[0-9]+]], 0($[[R2]])
; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]]
; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]]
; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; ALL: sc $[[R14]], 0($[[R2]])
; NOT-MICROMIPS: beqz $[[R14]], [[BB0]]
; MICROMIPS: beqzc $[[R14]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]]
; MICROMIPS: beqzc $[[R14]], $[[BB0]]
; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]]
; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]]
@ -438,10 +438,10 @@ entry:
; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)(
; ALL: addiu $[[PTR:[0-9]+]], $[[R0]], 1024
; ALL: [[BB0:(\$|.L)[A-Z_0-9]+]]:
; ALL: $[[BB0:[A-Z_0-9]+]]:
; ALL: ll $[[R1:[0-9]+]], 0($[[PTR]])
; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4
; ALL: sc $[[R2]], 0($[[PTR]])
; NOT-MICROMIPS: beqz $[[R2]], [[BB0]]
; MICROMIPS: beqzc $[[R2]], [[BB0]]
; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]]
; MICROMIPS: beqzc $[[R2]], $[[BB0]]
}

4
llvm/test/CodeGen/Mips/blez_bgez.ll
View File

@ -2,7 +2,7 @@
; RUN: llc -march=mips64el < %s | FileCheck %s
; CHECK-LABEL: test_blez:
; CHECK: blez ${{[0-9]+}}, {{(\$|.L)BB}}
; CHECK: blez ${{[0-9]+}}, $BB
define void @test_blez(i32 %a) {
entry:
@ -20,7 +20,7 @@ if.end:
declare void @foo1()
; CHECK-LABEL: test_bgez:
; CHECK: bgez ${{[0-9]+}}, {{(\$|.L)BB}}
; CHECK: bgez ${{[0-9]+}}, $BB
define void @test_bgez(i32 %a) {
entry:

48
llvm/test/CodeGen/Mips/blockaddr.ll
View File

@ -14,30 +14,30 @@ entry:
ret i8* %x
}
; PIC-O32: lw $[[R0:[0-9]+]], %got([[T0:(\$|.L)tmp[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo([[T0]])
; PIC-O32: lw $[[R1:[0-9]+]], %got([[T1:(\$|.L)tmp[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo([[T1]])
; STATIC-O32: lui $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]])
; STATIC-O32: lui $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]])
; PIC-N32: lw $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]])
; PIC-N32: lw $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]])
; STATIC-N32: lui $[[R2:[0-9]+]], %hi([[T2:(\$|.L)tmp[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo([[T2]])
; STATIC-N32: lui $[[R3:[0-9]+]], %hi([[T3:(\$|.L)tmp[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo([[T3]])
; PIC-N64: ld $[[R0:[0-9]+]], %got_page([[T0:(\$|.L)tmp[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst([[T0]])
; PIC-N64: ld $[[R1:[0-9]+]], %got_page([[T1:(\$|.L)tmp[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst([[T1]])
; STATIC-N64: ld $[[R2:[0-9]+]], %got_page([[T2:(\$|.L)tmp[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst([[T2]])
; STATIC-N64: ld $[[R3:[0-9]+]], %got_page([[T3:(\$|.L)tmp[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst([[T3]])
; PIC-O32: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]])
; PIC-O32: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])
; PIC-O32: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]])
; STATIC-O32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
; STATIC-O32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
; STATIC-O32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
; PIC-N32: lw $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
; PIC-N32: lw $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
; PIC-N32: addiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
; STATIC-N32: lui $[[R2:[0-9]+]], %hi($tmp[[T2:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T2]])
; STATIC-N32: lui $[[R3:[0-9]+]], %hi($tmp[[T3:[0-9]+]])
; STATIC-N32: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T3]])
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($tmp[[T0:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R0]], %got_ofst($tmp[[T0]])
; PIC-N64: ld $[[R1:[0-9]+]], %got_page($tmp[[T1:[0-9]+]])
; PIC-N64: daddiu ${{[0-9]+}}, $[[R1]], %got_ofst($tmp[[T1]])
; STATIC-N64: ld $[[R2:[0-9]+]], %got_page($tmp[[T2:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R2]], %got_ofst($tmp[[T2]])
; STATIC-N64: ld $[[R3:[0-9]+]], %got_page($tmp[[T3:[0-9]+]])
; STATIC-N64: daddiu ${{[0-9]+}}, $[[R3]], %got_ofst($tmp[[T3]])
; STATIC-MIPS16-1: .ent f
; STATIC-MIPS16-2: .ent f
; STATIC-MIPS16-1: li $[[R1_16:[0-9]+]], %hi($tmp[[TI_16:[0-9]+]])

24
llvm/test/CodeGen/Mips/fpbr.ll
View File

@ -11,14 +11,14 @@ entry:
; 32-FCC: c.eq.s $f12, $f14
; 64-FCC: c.eq.s $f12, $f13
; FCC: bc1f {{(\$|.L)BB0_2}}
; FCC: bc1f $BB0_2
; 32-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f14
; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; FIXME: We ought to be able to transform not+bnez -> beqz
; GPR: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], {{(\$|.L)BB0_2}}
; GPR: bnez $[[GPRCC]], $BB0_2
%cmp = fcmp oeq float %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@ -45,13 +45,13 @@ entry:
; 32-FCC: c.olt.s $f12, $f14
; 64-FCC: c.olt.s $f12, $f13
; FCC: bc1f {{(\$|.L)BB1_2}}
; FCC: bc1f $BB1_2
; 32-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], {{(\$|.L)BB1_2}}
; GPR: bnez $[[GPRCC]], $BB1_2
%cmp = fcmp olt float %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@ -74,13 +74,13 @@ entry:
; 32-FCC: c.ole.s $f12, $f14
; 64-FCC: c.ole.s $f12, $f13
; FCC: bc1t {{(\$|.L)BB2_2}}
; FCC: bc1t $BB2_2
; 32-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: beqz $[[GPRCC]], {{(\$|.L)BB2_2}}
; GPR: beqz $[[GPRCC]], $BB2_2
%cmp = fcmp ugt float %f2, %f3
br i1 %cmp, label %if.else, label %if.then
@ -103,14 +103,14 @@ entry:
; 32-FCC: c.eq.d $f12, $f14
; 64-FCC: c.eq.d $f12, $f13
; FCC: bc1f {{(\$|.L)BB3_2}}
; FCC: bc1f $BB3_2
; 32-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f14
; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; FIXME: We ought to be able to transform not+bnez -> beqz
; GPR: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], {{(\$|.L)BB3_2}}
; GPR: bnez $[[GPRCC]], $BB3_2
%cmp = fcmp oeq double %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@ -133,13 +133,13 @@ entry:
; 32-FCC: c.olt.d $f12, $f14
; 64-FCC: c.olt.d $f12, $f13
; FCC: bc1f {{(\$|.L)BB4_2}}
; FCC: bc1f $BB4_2
; 32-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: bnez $[[GPRCC]], {{(\$|.L)BB4_2}}
; GPR: bnez $[[GPRCC]], $BB4_2
%cmp = fcmp olt double %f2, %f3
br i1 %cmp, label %if.then, label %if.else
@ -162,13 +162,13 @@ entry:
; 32-FCC: c.ole.d $f12, $f14
; 64-FCC: c.ole.d $f12, $f13
; FCC: bc1t {{(\$|.L)BB5_2}}
; FCC: bc1t $BB5_2
; 32-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f14, $f12
; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12
; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]]
; GPR-NOT: not $[[GPRCC]], $[[GPRCC]]
; GPR: beqz $[[GPRCC]], {{(\$|.L)BB5_2}}
; GPR: beqz $[[GPRCC]], $BB5_2
%cmp = fcmp ugt double %f2, %f3
br i1 %cmp, label %if.else, label %if.then

16
llvm/test/CodeGen/Mips/llvm-ir/ashr.ll
View File

@ -88,18 +88,18 @@ entry:
; M2: srav $[[T0:[0-9]+]], $4, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
; M2: bnez $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: move $3, $[[T0]]
; M2: srlv $[[T2:[0-9]+]], $5, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: sll $[[T4:[0-9]+]], $4, 1
; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; M2: or $3, $[[T3]], $[[T2]]
; M2: [[BB0]]:
; M2: beqz $[[T1]], [[BB1:(\$|.L)BB[0-9_]+]]
; M2: $[[BB0]]:
; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]]
; M2: nop
; M2: sra $2, $4, 31
; M2: [[BB1]]:
; M2: $[[BB1]]:
; M2: jr $ra
; M2: nop
@ -146,18 +146,18 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrav $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], [[BB0:(\$|.L)BB[0-9_]+]]
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]]
; M3: [[BB0]]:
; M3: beqz $[[T3]], [[BB1:(\$|.L)BB[0-9_]+]]
; M3: $[[BB0]]:
; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: nop
; M3: dsra $2, $4, 63
; M3: [[BB1]]:
; M3: $[[BB1]]:
; M3: jr $ra
; M3: nop

4
llvm/test/CodeGen/Mips/llvm-ir/indirectbr.ll
View File

@ -17,12 +17,12 @@ define i32 @br(i8 *%addr) {
; NOT-R6: jr $4 # <MCInst #{{[0-9]+}} JR
; R6: jr $4 # <MCInst #{{[0-9]+}} JALR
; ALL: {{(\$|.L)BB0_1}}: # %L1
; ALL: $BB0_1: # %L1
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; ALL: addiu $2, $zero, 0
; ALL: {{(\$|.L)BB0_2}}: # %L2
; ALL: $BB0_2: # %L2
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; ALL: addiu $2, $zero, 1

8
llvm/test/CodeGen/Mips/llvm-ir/lshr.ll
View File

@ -140,18 +140,18 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsrlv $[[T1:[0-9]+]], $4, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], [[BB0:($|.L)BB[0-9_]+]]
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $3, $[[T1]]
; M3: dsrlv $[[T4:[0-9]+]], $5, $7
; M3: dsll $[[T5:[0-9]+]], $4, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $3, $[[T7]], $[[T4]]
; M3: [[BB0]]:
; M3: bnez $[[T3]], [[BB1:($|.L)BB[0-9_]+]]
; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $2, $zero, 0
; M3: move $2, $[[T1]]
; M3: [[BB1]]:
; M3: $[[BB1]]:
; M3: jr $ra
; M3: nop

92
llvm/test/CodeGen/Mips/llvm-ir/select.ll
View File

@ -35,10 +35,10 @@ entry:
; ALL-LABEL: tst_select_i1_i1:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2-M3: move $5, $6
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: move $2, $5
@ -60,10 +60,10 @@ entry:
; ALL-LABEL: tst_select_i1_i8:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2-M3: move $5, $6
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: move $2, $5
@ -85,10 +85,10 @@ entry:
; ALL-LABEL: tst_select_i1_i32:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2-M3: move $5, $6
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: move $2, $5
@ -110,10 +110,10 @@ entry:
; ALL-LABEL: tst_select_i1_i64:
; M2: andi $[[T0:[0-9]+]], $4, 1
; M2: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2: nop
; M2: lw $[[T1:[0-9]+]], 16($sp)
; M2: [[BB0]]:
; M2: $[[BB0]]:
; FIXME: This branch is redundant
; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]]
; M2: nop
@ -140,10 +140,10 @@ entry:
; SEL-32: or $3, $[[T4]], $[[T6]]
; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M3: nop
; M3: move $5, $6
; M3: [[BB0]]:
; M3: $[[BB0]]:
; M3: jr $ra
; M3: move $2, $5
@ -166,12 +166,12 @@ entry:
; ALL-LABEL: tst_select_i1_float:
; M2-M3: andi $[[T0:[0-9]+]], $4, 1
; M2-M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: jr $ra
; M2: mtc1 $6, $f0
; M3: mov.s $f13, $f14
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2: mtc1 $5, $f0
; M3: mov.s $f0, $f13
@ -202,11 +202,11 @@ entry:
; ALL-LABEL: tst_select_i1_float_reordered:
; M2-M3: andi $[[T0:[0-9]+]], $6, 1
; M2-M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -232,12 +232,12 @@ entry:
; ALL-LABEL: tst_select_i1_double:
; M2: andi $[[T0:[0-9]+]], $4, 1
; M2: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M2: nop
; M2: ldc1 $f0, 16($sp)
; M2: jr $ra
; M2: nop
; M2: [[BB0]]:
; M2: $[[BB0]]:
; M2: mtc1 $7, $f0
; M2: jr $ra
; M2: mtc1 $6, $f1
@ -256,10 +256,10 @@ entry:
; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
; M3: andi $[[T0:[0-9]+]], $4, 1
; M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M3: nop
; M3: mov.d $f13, $f14
; M3: [[BB0]]:
; M3: $[[BB0]]:
; M3: jr $ra
; M3: mov.d $f0, $f13
@ -280,10 +280,10 @@ entry:
; M2: lw $[[T0:[0-9]+]], 16($sp)
; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
; M2: bnez $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: nop
; M2: mov.d $f12, $f14
; M2: [[BB0]]:
; M2: $[[BB0]]:
; M2: jr $ra
; M2: mov.d $f0, $f12
@ -297,10 +297,10 @@ entry:
; SEL-32: sel.d $f0, $f14, $f12
; M3: andi $[[T0:[0-9]+]], $6, 1
; M3: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
; M3: nop
; M3: mov.d $f12, $f13
; M3: [[BB0]]:
; M3: $[[BB0]]:
; M3: jr $ra
; M3: mov.d $f0, $f12
@ -320,11 +320,11 @@ entry:
; M2: c.olt.s $f12, $f14
; M3: c.olt.s $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -352,11 +352,11 @@ entry:
; M2: c.ole.s $f12, $f14
; M3: c.ole.s $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -384,11 +384,11 @@ entry:
; M2: c.ule.s $f12, $f14
; M3: c.ule.s $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -416,11 +416,11 @@ entry:
; M2: c.ult.s $f12, $f14
; M3: c.ult.s $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -448,11 +448,11 @@ entry:
; M2: c.eq.s $f12, $f14
; M3: c.eq.s $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -480,11 +480,11 @@ entry:
; M2: c.ueq.s $f12, $f14
; M3: c.ueq.s $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.s $f12, $f14
; M3: mov.s $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.s $f0, $f12
@ -519,11 +519,11 @@ entry:
; M2: c.olt.d $f12, $f14
; M3: c.olt.d $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12
@ -551,11 +551,11 @@ entry:
; M2: c.ole.d $f12, $f14
; M3: c.ole.d $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12
@ -583,11 +583,11 @@ entry:
; M2: c.ule.d $f12, $f14
; M3: c.ule.d $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12
@ -615,11 +615,11 @@ entry:
; M2: c.ult.d $f12, $f14
; M3: c.ult.d $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12
@ -647,11 +647,11 @@ entry:
; M2: c.eq.d $f12, $f14
; M3: c.eq.d $f12, $f13
; M2-M3: bc1t [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12
@ -679,11 +679,11 @@ entry:
; M2: c.ueq.d $f12, $f14
; M3: c.ueq.d $f12, $f13
; M2-M3: bc1f [[BB0:(\$|.L)BB[0-9_]+]]
; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
; M2-M3: nop
; M2: mov.d $f12, $f14
; M3: mov.d $f12, $f13
; M2-M3: [[BB0]]:
; M2-M3: $[[BB0]]:
; M2-M3: jr $ra
; M2-M3: mov.d $f0, $f12

16
llvm/test/CodeGen/Mips/llvm-ir/shl.ll
View File

@ -98,18 +98,18 @@ entry:
; M2: sllv $[[T0:[0-9]+]], $5, $7
; M2: andi $[[T1:[0-9]+]], $7, 32
; M2: bnez $[[T1]], [[BB0:(\$|.L)BB[0-9_]+]]
; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
; M2: move $2, $[[T0]]
; M2: sllv $[[T2:[0-9]+]], $4, $7
; M2: not $[[T3:[0-9]+]], $7
; M2: srl $[[T4:[0-9]+]], $5, 1
; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]]
; M2: or $2, $[[T2]], $[[T3]]
; M2: [[BB0]]:
; M2: bnez $[[T1]], [[BB1:(\$|.L)BB[0-9_]+]]
; M2: $[[BB0]]:
; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]]
; M2: addiu $3, $zero, 0
; M2: move $3, $[[T0]]
; M2: [[BB1]]:
; M2: $[[BB1]]:
; M2: jr $ra
; M2: nop
@ -152,18 +152,18 @@ entry:
; M3: sll $[[T0:[0-9]+]], $7, 0
; M3: dsllv $[[T1:[0-9]+]], $5, $7
; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
; M3: bnez $[[T3:[0-9]+]], [[BB0:(\$|.L)BB[0-9_]+]]
; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]]
; M3: move $2, $[[T1]]
; M3: dsllv $[[T4:[0-9]+]], $4, $7
; M3: dsrl $[[T5:[0-9]+]], $5, 1
; M3: not $[[T6:[0-9]+]], $[[T0]]
; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]]
; M3: or $2, $[[T4]], $[[T7]]
; M3: [[BB0]]:
; M3: bnez $[[T3]], [[BB1:(\$|.L)BB[0-9_]+]]
; M3: $[[BB0]]:
; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]]
; M3: daddiu $3, $zero, 0
; M3: move $3, $[[T1]]
; M3: [[BB1]]:
; M3: $[[BB1]]:
; M3: jr $ra
; M3: nop

60
llvm/test/CodeGen/Mips/longbranch.ll
View File

@ -31,12 +31,12 @@ end:
; CHECK: lui $[[R0:[0-9]+]], %hi(_gp_disp)
; CHECK: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
; CHECK: beqz $4, [[BB0:(\$|.L)BB[0-9_]+]]
; CHECK: beqz $4, $[[BB0:BB[0-9_]+]]
; CHECK: addu $[[GP:[0-9]+]], $[[R0]], $25
; CHECK: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; CHECK: addiu $[[R2:[0-9]+]], $zero, 1
; CHECK: sw $[[R2]], 0($[[R1]])
; CHECK: [[BB0]]:
; CHECK: $[[BB0]]:
; CHECK: jr $ra
; CHECK: nop
@ -49,26 +49,26 @@ end:
; O32: lui $[[R0:[0-9]+]], %hi(_gp_disp)
; O32: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
; O32: bnez $4, [[BB0:(\$|.L)BB[0-9_]+]]
; O32: bnez $4, $[[BB0:BB[0-9_]+]]
; O32: addu $[[GP:[0-9]+]], $[[R0]], $25
; Check for long branch expansion:
; O32: addiu $sp, $sp, -8
; O32-NEXT: sw $ra, 0($sp)
; O32-NEXT: lui $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
; O32-NEXT: bal [[BB1]]
; O32-NEXT: addiu $1, $1, %lo(([[BB2]])-([[BB1]]))
; O32-NEXT: [[BB1]]:
; O32-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
; O32-NEXT: bal $[[BB1]]
; O32-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
; O32-NEXT: $[[BB1]]:
; O32-NEXT: addu $1, $ra, $1
; O32-NEXT: lw $ra, 0($sp)
; O32-NEXT: jr $1
; O32-NEXT: addiu $sp, $sp, 8
; O32: [[BB0]]:
; O32: $[[BB0]]:
; O32: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; O32: addiu $[[R2:[0-9]+]], $zero, 1
; O32: sw $[[R2]], 0($[[R1]])
; O32: [[BB2]]:
; O32: $[[BB2]]:
; O32: jr $ra
; O32: nop
@ -76,28 +76,28 @@ end:
; Check the MIPS64 version.
; N64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(test1)))
; N64: bnez $4, [[BB0:(\$|.L)BB[0-9_]+]]
; N64: bnez $4, $[[BB0:BB[0-9_]+]]
; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25
; Check for long branch expansion:
; N64: daddiu $sp, $sp, -16
; N64-NEXT: sd $ra, 0($sp)
; N64-NEXT: daddiu $1, $zero, %hi([[BB2:(\$|.L)BB[0-9_]+]]-[[BB1:(\$|.L)BB[0-9_]+]])
; N64-NEXT: daddiu $1, $zero, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
; N64-NEXT: dsll $1, $1, 16
; N64-NEXT: bal [[BB1]]
; N64-NEXT: daddiu $1, $1, %lo([[BB2]]-[[BB1]])
; N64-NEXT: [[BB1]]:
; N64-NEXT: bal $[[BB1]]
; N64-NEXT: daddiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
; N64-NEXT: $[[BB1]]:
; N64-NEXT: daddu $1, $ra, $1
; N64-NEXT: ld $ra, 0($sp)
; N64-NEXT: jr $1
; N64-NEXT: daddiu $sp, $sp, 16
; N64: [[BB0]]:
; N64: $[[BB0]]:
; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1)))
; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]])
; N64: addiu $[[R3:[0-9]+]], $zero, 1
; N64: sw $[[R3]], 0($[[R2]])
; N64: [[BB2]]:
; N64: $[[BB2]]:
; N64: jr $ra
; N64: nop
@ -106,26 +106,26 @@ end:
; MICROMIPS: lui $[[R0:[0-9]+]], %hi(_gp_disp)
; MICROMIPS: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
; MICROMIPS: bnez $4, [[BB0:(\$|.L)BB[0-9_]+]]
; MICROMIPS: bnez $4, $[[BB0:BB[0-9_]+]]
; MICROMIPS: addu $[[GP:[0-9]+]], $[[R0]], $25
; Check for long branch expansion:
; MICROMIPS: addiu $sp, $sp, -8
; MICROMIPS-NEXT: sw $ra, 0($sp)
; MICROMIPS-NEXT: lui $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
; MICROMIPS-NEXT: bal [[BB1]]
; MICROMIPS-NEXT: addiu $1, $1, %lo(([[BB2]])-([[BB1]]))
; MICROMIPS-NEXT: [[BB1]]:
; MICROMIPS-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
; MICROMIPS-NEXT: bal $[[BB1]]
; MICROMIPS-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
; MICROMIPS-NEXT: $[[BB1]]:
; MICROMIPS-NEXT: addu $1, $ra, $1
; MICROMIPS-NEXT: lw $ra, 0($sp)
; MICROMIPS-NEXT: jr $1
; MICROMIPS-NEXT: addiu $sp, $sp, 8
; MICROMIPS: [[BB0]]:
; MICROMIPS: $[[BB0]]:
; MICROMIPS: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; MICROMIPS: li16 $[[R2:[0-9]+]], 1
; MICROMIPS: sw16 $[[R2]], 0($[[R1]])
; MICROMIPS: [[BB2]]:
; MICROMIPS: $[[BB2]]:
; MICROMIPS: jrc $ra
@ -135,28 +135,28 @@ end:
; NACL: lui $[[R0:[0-9]+]], %hi(_gp_disp)
; NACL: addiu $[[R0]], $[[R0]], %lo(_gp_disp)
; NACL: bnez $4, [[BB0:(\$|.L)BB[0-9_]+]]
; NACL: bnez $4, $[[BB0:BB[0-9_]+]]
; NACL: addu $[[GP:[0-9]+]], $[[R0]], $25
; Check for long branch expansion:
; NACL: addiu $sp, $sp, -8
; NACL-NEXT: sw $ra, 0($sp)
; NACL-NEXT: lui $1, %hi(([[BB2:(\$|.L)BB[0-9_]+]])-([[BB1:(\$|.L)BB[0-9_]+]]))
; NACL-NEXT: bal [[BB1]]
; NACL-NEXT: addiu $1, $1, %lo(([[BB2]])-([[BB1]]))
; NACL-NEXT: [[BB1]]:
; NACL-NEXT: lui $1, %hi(($[[BB2:BB[0-9_]+]])-($[[BB1:BB[0-9_]+]]))
; NACL-NEXT: bal $[[BB1]]
; NACL-NEXT: addiu $1, $1, %lo(($[[BB2]])-($[[BB1]]))
; NACL-NEXT: $[[BB1]]:
; NACL-NEXT: addu $1, $ra, $1
; NACL-NEXT: lw $ra, 0($sp)
; NACL-NEXT: addiu $sp, $sp, 8
; NACL-NEXT: jr $1
; NACL-NEXT: nop
; NACL: [[BB0]]:
; NACL: $[[BB0]]:
; NACL: lw $[[R1:[0-9]+]], %got(x)($[[GP]])
; NACL: addiu $[[R2:[0-9]+]], $zero, 1
; NACL: sw $[[R2]], 0($[[R1]])
; NACL: .align 4
; NACL-NEXT: [[BB2]]:
; NACL-NEXT: $[[BB2]]:
; NACL: jr $ra
; NACL: nop
}

16
llvm/test/CodeGen/Mips/octeon.ll
View File

@ -91,9 +91,9 @@ entry:
define i64 @bbit0(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit0:
; OCTEON: bbit0 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: bnez $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 8
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
@ -107,11 +107,11 @@ endif:
define i64 @bbit032(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit032:
; OCTEON: bbit032 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
; MIPS64: bnez $[[T2]], [[BB0:(\$|.L)BB[0-9_]+]]
; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 34359738368
%res = icmp eq i64 %bit, 0
br i1 %res, label %endif, label %if
@ -125,9 +125,9 @@ endif:
define i64 @bbit1(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit1:
; OCTEON: bbit1 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
; MIPS64: andi $[[T0:[0-9]+]], $4, 8
; MIPS64: beqz $[[T0]], [[BB0:(\$|.L)BB[0-9_]+]]
; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 8
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if
@ -141,11 +141,11 @@ endif:
define i64 @bbit132(i64 %a) nounwind {
entry:
; ALL-LABEL: bbit132:
; OCTEON: bbit132 $4, 3, [[BB0:(\$|.L)BB[0-9_]+]]
; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
; MIPS64: beqz $[[T2]], [[BB0:(\$|.L)BB[0-9_]+]]
; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
%bit = and i64 %a, 34359738368
%res = icmp ne i64 %bit, 0
br i1 %res, label %endif, label %if

11
llvm/test/CodeGen/Mips/private_label.ll
View File

@ -1,11 +0,0 @@
; RUN: llc -march=mips < %s | FileCheck -check-prefix=O32 %s
; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck -check-prefix=N32 %s
; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck -check-prefix=N64 %s
define void @labels() nounwind {
entry:
; O32: $func_end
; N32: .Lfunc_end
; N64: .Lfunc_end
ret void
}