forked from OSchip/llvm-project
[AArch64AsmParser] rewrite of function parseSysAlias
This is a cleanup/rewrite of the parseSysAlias function. It was not using the tablegen instruction descriptions, but was “manually” matching the mnemonics and recreating the operands whereas all this information is already in tablegen; all this code has been replaced with calls to lookupXYZByName tablegen calls. Differential Revision: https://reviews.llvm.org/D30491 llvm-svn: 296857
This commit is contained in:
Sjoerd Meijer
parent
321cf3c650
commit
69bccf96bd
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@ -74,6 +74,7 @@ private:
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SMLoc getLoc() const { return getParser().getTok().getLoc(); }
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bool parseSysAlias(StringRef Name, SMLoc NameLoc, OperandVector &Operands);
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void createSysAlias(uint16_t Encoding, OperandVector &Operands, SMLoc S);
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AArch64CC::CondCode parseCondCodeString(StringRef Cond);
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bool parseCondCode(OperandVector &Operands, bool invertCondCode);
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unsigned matchRegisterNameAlias(StringRef Name, bool isVector);
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@ -2333,6 +2334,35 @@ AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
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return MatchOperand_Success;
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}
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static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
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if (FBS[AArch64::HasV8_1aOps])
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Str += "ARMv8.1a";
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else if (FBS[AArch64::HasV8_2aOps])
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Str += "ARMv8.2a";
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else
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Str += "(unknown)";
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}
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void AArch64AsmParser::createSysAlias(uint16_t Encoding, OperandVector &Operands,
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SMLoc S) {
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const uint16_t Op2 = Encoding & 7;
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const uint16_t Cm = (Encoding & 0x78) >> 3;
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const uint16_t Cn = (Encoding & 0x780) >> 7;
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const uint16_t Op1 = (Encoding & 0x3800) >> 11;
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const MCExpr *Expr = MCConstantExpr::create(Op1, getContext());
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Operands.push_back(
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AArch64Operand::CreateImm(Expr, S, getLoc(), getContext()));
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Operands.push_back(
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AArch64Operand::CreateSysCR(Cn, S, getLoc(), getContext()));
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Operands.push_back(
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AArch64Operand::CreateSysCR(Cm, S, getLoc(), getContext()));
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Expr = MCConstantExpr::create(Op2, getContext());
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Operands.push_back(
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AArch64Operand::CreateImm(Expr, S, getLoc(), getContext()));
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}
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/// parseSysAlias - The IC, DC, AT, and TLBI instructions are simple aliases for
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/// the SYS instruction. Parse them specially so that we create a SYS MCInst.
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bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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@ -2349,228 +2379,48 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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StringRef Op = Tok.getString();
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SMLoc S = Tok.getLoc();
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const MCExpr *Expr = nullptr;
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#define SYS_ALIAS(op1, Cn, Cm, op2) \
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do { \
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Expr = MCConstantExpr::create(op1, getContext()); \
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Operands.push_back( \
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AArch64Operand::CreateImm(Expr, S, getLoc(), getContext())); \
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Operands.push_back( \
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AArch64Operand::CreateSysCR(Cn, S, getLoc(), getContext())); \
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Operands.push_back( \
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AArch64Operand::CreateSysCR(Cm, S, getLoc(), getContext())); \
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Expr = MCConstantExpr::create(op2, getContext()); \
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Operands.push_back( \
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AArch64Operand::CreateImm(Expr, S, getLoc(), getContext())); \
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} while (false)
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if (Mnemonic == "ic") {
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if (!Op.compare_lower("ialluis")) {
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// SYS #0, C7, C1, #0
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SYS_ALIAS(0, 7, 1, 0);
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} else if (!Op.compare_lower("iallu")) {
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// SYS #0, C7, C5, #0
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SYS_ALIAS(0, 7, 5, 0);
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} else if (!Op.compare_lower("ivau")) {
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// SYS #3, C7, C5, #1
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SYS_ALIAS(3, 7, 5, 1);
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} else {
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const AArch64IC::IC *IC = AArch64IC::lookupICByName(Op);
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if (!IC)
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return TokError("invalid operand for IC instruction");
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else if (!IC->haveFeatures(getSTI().getFeatureBits())) {
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std::string Str("IC " + std::string(IC->Name) + " requires ");
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setRequiredFeatureString(IC->getRequiredFeatures(), Str);
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return TokError(Str.c_str());
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}
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createSysAlias(IC->Encoding, Operands, S);
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} else if (Mnemonic == "dc") {
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if (!Op.compare_lower("zva")) {
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// SYS #3, C7, C4, #1
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SYS_ALIAS(3, 7, 4, 1);
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} else if (!Op.compare_lower("ivac")) {
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// SYS #3, C7, C6, #1
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SYS_ALIAS(0, 7, 6, 1);
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} else if (!Op.compare_lower("isw")) {
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// SYS #0, C7, C6, #2
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SYS_ALIAS(0, 7, 6, 2);
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} else if (!Op.compare_lower("cvac")) {
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// SYS #3, C7, C10, #1
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SYS_ALIAS(3, 7, 10, 1);
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} else if (!Op.compare_lower("csw")) {
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// SYS #0, C7, C10, #2
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SYS_ALIAS(0, 7, 10, 2);
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} else if (!Op.compare_lower("cvau")) {
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// SYS #3, C7, C11, #1
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SYS_ALIAS(3, 7, 11, 1);
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} else if (!Op.compare_lower("civac")) {
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// SYS #3, C7, C14, #1
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SYS_ALIAS(3, 7, 14, 1);
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} else if (!Op.compare_lower("cisw")) {
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// SYS #0, C7, C14, #2
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SYS_ALIAS(0, 7, 14, 2);
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} else if (!Op.compare_lower("cvap")) {
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if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
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// SYS #3, C7, C12, #1
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SYS_ALIAS(3, 7, 12, 1);
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} else {
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return TokError("DC CVAP requires ARMv8.2a");
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}
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} else {
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const AArch64DC::DC *DC = AArch64DC::lookupDCByName(Op);
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if (!DC)
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return TokError("invalid operand for DC instruction");
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else if (!DC->haveFeatures(getSTI().getFeatureBits())) {
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std::string Str("DC " + std::string(DC->Name) + " requires ");
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setRequiredFeatureString(DC->getRequiredFeatures(), Str);
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return TokError(Str.c_str());
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}
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createSysAlias(DC->Encoding, Operands, S);
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} else if (Mnemonic == "at") {
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if (!Op.compare_lower("s1e1r")) {
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// SYS #0, C7, C8, #0
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SYS_ALIAS(0, 7, 8, 0);
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} else if (!Op.compare_lower("s1e2r")) {
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// SYS #4, C7, C8, #0
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SYS_ALIAS(4, 7, 8, 0);
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} else if (!Op.compare_lower("s1e3r")) {
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// SYS #6, C7, C8, #0
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SYS_ALIAS(6, 7, 8, 0);
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} else if (!Op.compare_lower("s1e1w")) {
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// SYS #0, C7, C8, #1
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SYS_ALIAS(0, 7, 8, 1);
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} else if (!Op.compare_lower("s1e2w")) {
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// SYS #4, C7, C8, #1
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SYS_ALIAS(4, 7, 8, 1);
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} else if (!Op.compare_lower("s1e3w")) {
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// SYS #6, C7, C8, #1
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SYS_ALIAS(6, 7, 8, 1);
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} else if (!Op.compare_lower("s1e0r")) {
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// SYS #0, C7, C8, #3
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SYS_ALIAS(0, 7, 8, 2);
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} else if (!Op.compare_lower("s1e0w")) {
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// SYS #0, C7, C8, #3
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SYS_ALIAS(0, 7, 8, 3);
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} else if (!Op.compare_lower("s12e1r")) {
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// SYS #4, C7, C8, #4
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SYS_ALIAS(4, 7, 8, 4);
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} else if (!Op.compare_lower("s12e1w")) {
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// SYS #4, C7, C8, #5
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SYS_ALIAS(4, 7, 8, 5);
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} else if (!Op.compare_lower("s12e0r")) {
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// SYS #4, C7, C8, #6
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SYS_ALIAS(4, 7, 8, 6);
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} else if (!Op.compare_lower("s12e0w")) {
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// SYS #4, C7, C8, #7
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SYS_ALIAS(4, 7, 8, 7);
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} else if (!Op.compare_lower("s1e1rp")) {
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if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
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// SYS #0, C7, C9, #0
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SYS_ALIAS(0, 7, 9, 0);
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} else {
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return TokError("AT S1E1RP requires ARMv8.2a");
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}
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} else if (!Op.compare_lower("s1e1wp")) {
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if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
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// SYS #0, C7, C9, #1
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SYS_ALIAS(0, 7, 9, 1);
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} else {
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return TokError("AT S1E1WP requires ARMv8.2a");
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}
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} else {
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const AArch64AT::AT *AT = AArch64AT::lookupATByName(Op);
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if (!AT)
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return TokError("invalid operand for AT instruction");
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else if (!AT->haveFeatures(getSTI().getFeatureBits())) {
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std::string Str("AT " + std::string(AT->Name) + " requires ");
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setRequiredFeatureString(AT->getRequiredFeatures(), Str);
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return TokError(Str.c_str());
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}
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createSysAlias(AT->Encoding, Operands, S);
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} else if (Mnemonic == "tlbi") {
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if (!Op.compare_lower("vmalle1is")) {
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// SYS #0, C8, C3, #0
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SYS_ALIAS(0, 8, 3, 0);
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} else if (!Op.compare_lower("alle2is")) {
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// SYS #4, C8, C3, #0
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SYS_ALIAS(4, 8, 3, 0);
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} else if (!Op.compare_lower("alle3is")) {
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// SYS #6, C8, C3, #0
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SYS_ALIAS(6, 8, 3, 0);
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} else if (!Op.compare_lower("vae1is")) {
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// SYS #0, C8, C3, #1
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SYS_ALIAS(0, 8, 3, 1);
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} else if (!Op.compare_lower("vae2is")) {
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// SYS #4, C8, C3, #1
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SYS_ALIAS(4, 8, 3, 1);
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} else if (!Op.compare_lower("vae3is")) {
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// SYS #6, C8, C3, #1
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SYS_ALIAS(6, 8, 3, 1);
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} else if (!Op.compare_lower("aside1is")) {
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// SYS #0, C8, C3, #2
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SYS_ALIAS(0, 8, 3, 2);
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} else if (!Op.compare_lower("vaae1is")) {
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// SYS #0, C8, C3, #3
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SYS_ALIAS(0, 8, 3, 3);
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} else if (!Op.compare_lower("alle1is")) {
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// SYS #4, C8, C3, #4
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SYS_ALIAS(4, 8, 3, 4);
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} else if (!Op.compare_lower("vale1is")) {
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// SYS #0, C8, C3, #5
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SYS_ALIAS(0, 8, 3, 5);
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} else if (!Op.compare_lower("vaale1is")) {
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// SYS #0, C8, C3, #7
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SYS_ALIAS(0, 8, 3, 7);
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} else if (!Op.compare_lower("vmalle1")) {
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// SYS #0, C8, C7, #0
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SYS_ALIAS(0, 8, 7, 0);
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} else if (!Op.compare_lower("alle2")) {
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// SYS #4, C8, C7, #0
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SYS_ALIAS(4, 8, 7, 0);
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} else if (!Op.compare_lower("vale2is")) {
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// SYS #4, C8, C3, #5
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SYS_ALIAS(4, 8, 3, 5);
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} else if (!Op.compare_lower("vale3is")) {
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// SYS #6, C8, C3, #5
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SYS_ALIAS(6, 8, 3, 5);
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} else if (!Op.compare_lower("alle3")) {
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// SYS #6, C8, C7, #0
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SYS_ALIAS(6, 8, 7, 0);
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} else if (!Op.compare_lower("vae1")) {
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// SYS #0, C8, C7, #1
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SYS_ALIAS(0, 8, 7, 1);
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} else if (!Op.compare_lower("vae2")) {
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// SYS #4, C8, C7, #1
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SYS_ALIAS(4, 8, 7, 1);
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} else if (!Op.compare_lower("vae3")) {
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// SYS #6, C8, C7, #1
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SYS_ALIAS(6, 8, 7, 1);
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} else if (!Op.compare_lower("aside1")) {
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// SYS #0, C8, C7, #2
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SYS_ALIAS(0, 8, 7, 2);
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} else if (!Op.compare_lower("vaae1")) {
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// SYS #0, C8, C7, #3
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SYS_ALIAS(0, 8, 7, 3);
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} else if (!Op.compare_lower("alle1")) {
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// SYS #4, C8, C7, #4
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SYS_ALIAS(4, 8, 7, 4);
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} else if (!Op.compare_lower("vale1")) {
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// SYS #0, C8, C7, #5
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SYS_ALIAS(0, 8, 7, 5);
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} else if (!Op.compare_lower("vale2")) {
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// SYS #4, C8, C7, #5
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SYS_ALIAS(4, 8, 7, 5);
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} else if (!Op.compare_lower("vale3")) {
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// SYS #6, C8, C7, #5
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SYS_ALIAS(6, 8, 7, 5);
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} else if (!Op.compare_lower("vaale1")) {
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// SYS #0, C8, C7, #7
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SYS_ALIAS(0, 8, 7, 7);
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} else if (!Op.compare_lower("ipas2e1")) {
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// SYS #4, C8, C4, #1
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SYS_ALIAS(4, 8, 4, 1);
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} else if (!Op.compare_lower("ipas2le1")) {
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// SYS #4, C8, C4, #5
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SYS_ALIAS(4, 8, 4, 5);
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} else if (!Op.compare_lower("ipas2e1is")) {
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// SYS #4, C8, C4, #1
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SYS_ALIAS(4, 8, 0, 1);
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} else if (!Op.compare_lower("ipas2le1is")) {
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// SYS #4, C8, C4, #5
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SYS_ALIAS(4, 8, 0, 5);
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} else if (!Op.compare_lower("vmalls12e1")) {
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// SYS #4, C8, C7, #6
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SYS_ALIAS(4, 8, 7, 6);
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} else if (!Op.compare_lower("vmalls12e1is")) {
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// SYS #4, C8, C3, #6
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SYS_ALIAS(4, 8, 3, 6);
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} else {
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const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByName(Op);
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if (!TLBI)
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return TokError("invalid operand for TLBI instruction");
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else if (!TLBI->haveFeatures(getSTI().getFeatureBits())) {
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std::string Str("TLBI " + std::string(TLBI->Name) + " requires ");
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setRequiredFeatureString(TLBI->getRequiredFeatures(), Str);
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return TokError(Str.c_str());
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}
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createSysAlias(TLBI->Encoding, Operands, S);
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}
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#undef SYS_ALIAS
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Parser.Lex(); // Eat operand.
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bool ExpectRegister = (Op.lower().find("all") == StringRef::npos);
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@ -2583,12 +2433,10 @@ bool AArch64AsmParser::parseSysAlias(StringRef Name, SMLoc NameLoc,
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HasRegister = true;
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}
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if (ExpectRegister && !HasRegister) {
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if (ExpectRegister && !HasRegister)
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return TokError("specified " + Mnemonic + " op requires a register");
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}
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else if (!ExpectRegister && HasRegister) {
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else if (!ExpectRegister && HasRegister)
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return TokError("specified " + Mnemonic + " op does not use a register");
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}
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if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
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return true;
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@ -278,6 +278,8 @@ struct SysAlias {
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bool haveFeatures(FeatureBitset ActiveFeatures) const {
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return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
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}
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FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
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};
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struct SysAliasReg : SysAlias {
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